Manufacturing method of advanced node rear-section metal through hole

A technology of metal vias and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve problems affecting yield, increasing costs, and metal wire breakage

Inactive Publication Date: 2020-08-21
NANJING CHENGXIN INTEGRATED CIRCUIT TECH RES INST CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] Due to strict design rules, the via holes on two or three adjacent metal lines need to be pattern split into two or three photolithographic masks, which greatly affects the process efficiency. The cost is increased, and the open size of the hard mask is extremely small after the photolithography process, and it is easy to cause the problem of incomplete opening of the via hole and the disconnection between the metal lines in the etching process, resulting in defects and process windows. Small, affecting the yield

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  • Manufacturing method of advanced node rear-section metal through hole
  • Manufacturing method of advanced node rear-section metal through hole
  • Manufacturing method of advanced node rear-section metal through hole

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Embodiment Construction

[0032] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0033] In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0034] see figure 1 , the present invention provides a method for manufacturing an advanced node rear metal through hole, comprising:

[0035] S101. Manufacture a first metal layer by self-alignment double imaging or damascene process.

[0036] Specifically, the method for manufacturing the first metal layer by self-aligned double patterning (SADP, Self-aligned Double Patterning) process is as follows: aft...

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Abstract

The invention discloses a manufacturing method of an advanced node rear-section metal through hole. The method comprises: manufacturing a first metal layer through a self-alignment dual imaging or Damascus process; sequentially depositing a cover layer, an etching stop layer and a low-k dielectric layer on a substrate; manufacturing a second metal channel through self-alignment dual imaging or Damascus process again; combing a plurality of through holes into a rectangle; etching by utilizing a load effect; after an etching stop layer is etched, removing the etching stop layer through a wet method, and etching the over layer; opening the through holes, and enlarging a process window; and finally carrying out metal filling on the second metal channel and the through holes through a Damascusprocess to complete the through hole manufacturing. According to the invention, the process window is enlarged, and the yield is increased.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a method for manufacturing advanced node rear-stage metal vias. Background technique [0002] Due to strict design rules, the via holes on two or three adjacent metal lines need to be pattern split into two or three photolithographic masks, which greatly affects the process efficiency. The cost is increased, and the open size of the hard mask is extremely small after the photolithography process, and it is easy to cause the problem of incomplete opening of the via hole and the disconnection between the metal lines in the etching process, resulting in defects and process windows. Small, affecting the yield. Contents of the invention [0003] The purpose of the present invention is to provide a method for manufacturing through-holes in the back stage of advanced nodes, which can expand the process window and improve the yield. [0004] In order to achi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L21/76877H01L21/76897
Inventor 陈睿都安彦韦亚一粟雅娟杨红董立松张利斌苏晓菁王文武
Owner NANJING CHENGXIN INTEGRATED CIRCUIT TECH RES INST CO LTD
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