Method for improving chip hard macro power supply reliability
A reliability and chip technology, applied in the field of microelectronics, can solve the problems of poor robustness, affecting chip performance, and the reliability of hard macro power supply cannot be guaranteed.
Active Publication Date: 2020-08-25
ANHUI DONGKE SEMICON CO LTD
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Problems solved by technology
[0004] The robustness of this power supply network structure is poor. Under special or extreme conditions, the power supply reliability of the hard macro cannot be guaranteed, which may affect the performance of the entire chip.
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[0025] In integrated circuit design, with the continuous reduction of chip area and the continuous improvement of chip design in timing and logic complexity requirements, the feature size of the chip is continuously reduced. Under different processes, the number of available metal layers of the chip is also different. For example, typically, in the 0.18um process, the available metal layers are usually 4, 5, 6 layers, in the 0.13um process, generally 4-8 layers are optional, and in the 65nm process, the optional metal layers reach Up to 11 floors. Typically, the chip's power network occupies the top few metal layers of the chip.
[0026] In the chip, the logic of the hard macro has been integrated within itself, and it can be called according to the process library. Therefore, in some processes, there may be one or several metal layers above the hard macro that are not occupied by the chip power network. The embodiment of the present invention provides a method for improving...
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The invention discloses a method for improving chip hard macro power supply reliability. The method comprises the steps of determining a topological structure of a chip power supply network of a chipbased on design requirements of the chip and wiring resource constraints; wherein the topological structure of the chip power supply network comprises the number of metal layers, the number of generalwiring layers, the layer number of the metal layers of the general wiring layers, and the physical positions, directions, line widths and intervals of metal lines on each general wiring layer; determining a layer number of a universal wiring layer where a power supply pin in a hard macro of the chip is located; performing metal wire wiring of the hard macro special power supply network in one ormore metal layers except the general wiring layer above the general wiring layer in the hard macro; and according to the logic function of the hard macro, forming power supply through holes between two adjacent layers of metal wires in the hard macro special power supply network, between the metal wires of the hard macro special power supply network and the power supply ground pin and between themetal wires of the hard macro special power supply network and the chip power supply network, and communicating different layers of metal wires through the power supply through holes.
Description
technical field [0001] The invention relates to the field of microelectronics technology, in particular to a method for improving the reliability of chip hard macro power supply. Background technique [0002] In digital backend integrated circuit (IC) design, macro cell (Macro) is the most common unit in the design. Macro is a broad concept, usually we divide it into hard macro (Hard Macro) and soft macro (Soft Macro). Hard macros refer to specific functional modules, such as memory (Memory), phase-locked loop PLL, phase-locked loop DLL and other IP cores, which are used in application-specific integrated circuits (ASICs) or field programmable logic arrays (FPGAs). The pre-designed circuit function modules, the logic of the hard macro have been integrated in itself, and can be called according to the process library. [0003] In conventional digital circuit design, the hard macro is usually powered by the power mesh of the chip itself. The chip power mesh tiles the entire ...
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IPC IPC(8): G06F30/392G06F30/327
CPCG06F30/327G06F30/392
Inventor 赵少峰
Owner ANHUI DONGKE SEMICON CO LTD