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Current integration and charge sharing multi-bit convolution operation module with variable capacitance

A technology of convolution operation and capacitance capacity, which is applied in complex mathematical operations and other directions, and can solve the problems of complex digital processing control, large operation energy consumption, and high power consumption.

Active Publication Date: 2020-09-01
REEXEN TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the implementation methods of these multi-bit operations, multi-bit analog multipliers and accumulators have always been controlled by very complex digital processing, but in terms of quantization with low signal-to-noise ratios, traditional digital operations consume a lot of power compared to analog operations, so these Multi-bit operations under the control of digital processing will generate a lot of computing energy consumption
[0007] The binarized convolution proposed by CN201910068644 performs the XOR operation stage by modulating the control bus in the SRAM to realize the potential change, but the technical solution and teaching given in this patent require complex digital processing control, and the control module The requirements are high and consume too much energy

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  • Current integration and charge sharing multi-bit convolution operation module with variable capacitance
  • Current integration and charge sharing multi-bit convolution operation module with variable capacitance
  • Current integration and charge sharing multi-bit convolution operation module with variable capacitance

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Embodiment Construction

[0035] In order to make the object, principle, technical solution and advantages of the invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0036] It should be understood that, as stated in the summary of the present invention, the specific embodiments described here are used to explain the present invention, but the present invention can also be implemented in other ways than described here, and those skilled in the art can Similar extensions are made on the basis of the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0037] refer to figure 1 , for a general convolution operation as follows:

[0038] multi-digit binary number x i Formed input matrix, i from 1 to N; weight w ji The formed convolution kernel, j represents the corresponding jth window when i is determined; when the input constitutes an n*n...

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Abstract

The invention relates to an analog operation module, in particular to an analog operation module related to convolution operation, and provides a group of analog multipliers and accumulators (MAC). The current integration in the capacitor is used for multiplication of the convolution process of two multi-bit binary numbers; change of multiplier or multiplicand bit weight in a multiplication stageis realized by utilizing capacity double decreasing coding of capacitors with the same clock period, an addition process is realized by charge sharing among the capacitors, and the module has higher speed and the same unit clock during convolution operation and can be used for exchange delay or acceleration in an area. This idea is applicable to a series of binary bit number adjustable multi-bit convolution that can be used to achieve general convolution with two or more inputs. In particular, a bias arithmetic unit array may be added. The operation module can be used as a neural network convolution operation unit or a memory or near memory operation unit realized by operation accelerator hardware.

Description

technical field [0001] The invention relates to an analog operation module, in particular to an analog operation module related to convolution operation, and also relates to an analog calculation method for convolution operation. Background technique [0002] For the quantization of low signal-to-noise ratio, analog operation has higher efficiency than traditional digital operation. Therefore, digital quantities are usually converted into analog quantities before operation. Especially for neural networks, compared to its computational energy consumption, in the medium and large-scale hardware implementation of neural networks, since traditional data is stored in disks, data needs to be extracted into memory when performing operations, and this process requires a lot of I / O Storage connected to traditional memory tends to consume more power. However, based on analog memory and near-memory computing, the computing process can be sent to the data for local execution, which gre...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/15
CPCG06F17/15Y02D10/00
Inventor 阿隆索·莫尔加多刘洪杰
Owner REEXEN TECH CO LTD