A kind of 3D NAND memory and manufacturing method thereof

Abstract

The present invention provides a 3D NAND memory and a manufacturing method thereof. In the method, a stacked structure comprising a bottom sacrificial layer and alternately stacked sacrificial layers and insulating layers formed above the bottom sacrificial layer is formed on a substrate, and the bottom sacrificial layer is replaced by The source layer is oxidized, and a first isolation layer is formed on the surface of the source layer to realize the function of the back selection gate oxide. The method is beneficial to control the thickness of the first isolation layer and improve the uniformity of the first isolation layer, thereby facilitating the uniform inversion of the source electrode layer and ensuring the channel of electrons in the read and write operations of the memory. The thickness and uniformity of the source layer caused by the thickness of the back selection gate oxide layer are solved, and the continuity of the P-type well and the supply of holes during the erasing process can be realized. At the same time, the source layer is formed in the channel structure along the stacking direction, which increases the contact area between the source layer and the channel layer, and enhances the electrical connection between the source layer and the channel layer.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a 3D NAND memory and a manufacturing method thereof. Background technique [0002] As the feature size of devices in integrated circuits continues to shrink, 3D memory technologies that stack multiple planes of memory cells to achieve greater storage capacity and lower cost per bit are increasingly favored. 3D memory is a technology for stacking data units. Currently, more than 32 layers, or even 72, 96, 128 or more layers of data units can be stacked. As the number of stacked layers increases, the lead-out of the memory structure that runs through the stacked structure faces increasing challenges. [0003] The traditional method of realizing the communication between the channel structure and the substrate usually faces the problem of defects in the uniformity and continuity of the epitaxial structure, or the difficulty in controlling the thickness ...

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Problems solved by technology

[0003] The traditional method of realizing the communication between the channel structure and the substrate usually faces the problem of the uniformity and continuity of the epitaxial structure, or the difficulty of controlling the thickness of the back selection gate oxide.

In the multi-layer trench hole process, it will also face the problem of increased etching difficulty of the stacked structure

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