Convolutional interleaving and de-interleaving FPGA implementation method and system without redundant data
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A technology of convolutional interleaving and redundant data, applied in the field of digital signal transmission, can solve problems affecting system delay and system throughput
Active Publication Date: 2020-09-04
WUHAN GUIDE INFRARED CO LTD
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[0004] At present, the convolutional interleaving and deinterleaving based on FPGA are mostly to improve the relevant storage units, but no matter what kind of storage method, the current output of convolutional interleaving will contain redundant data, and the corresponding dein...
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Embodiment 1
[0057] This embodiment discloses a method for implementing convolutional interleaving and deinterleaving FPGA without redundant data, such as figure 1 ,include:
[0058] S100. Perform data splicing on the input data to obtain spliced new data;
[0059] Specifically, the specific method of the S100 is: adding invalid data 0 of a certain length 1 to the input data; the length 1 of the invalid data 0 is related to the branch number (B) and the branch length (L) in the interleaving principle, The specific conversion relationship is:
[0060] l=[(B-1)+(B-2)+...+1]*L
[0061] S200. Count the spliced new data valid signal by using the first counter to obtain a first count value;
[0062] Specifically, the S200 method is: counting the valid signals of the new data after splicing, counting the columns, rows, and blocks of the data respectively, the counting rule is to first count the columns, and count the columns The range is 0~B-1, when the value of the column count is equal ...
Embodiment 2
[0089] This embodiment discloses a convolutional interleaving and deinterleaving FPGA implementation system without redundant data. The specific system workflow block diagram is as follows Figure 4 , including: data splicing module, first counter module, first write RAM module, first read RAM module, first RAM storage module, second counter module, third counter module, second write RAM module, second read RAM module, the second RAM storage module.
[0090] The data splicing module performs data splicing on the input data to obtain spliced new data;
[0091] The first counter module counts the new data valid signals after the splicing to obtain the value of the first counter; specifically, the first counter module is divided into a column counter submodule, a row counter submodule, and a block counter submodule; Count the effective signals of the new data after splicing, and count the columns, rows, and blocks of the data respectively. The counting rule is to first count the...
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Abstract
The invention discloses a convolutional interleaving and de-interleaving FPGA implementation method and system without redundant data, and the method comprises the steps: carrying out the data splicing of input data, and obtaining spliced new data; counting the spliced new data effective signals through a first counter to obtain a first count value; separately generating a first write branch address and a first read branch address according to the first count value to obtain first output data subjected to convolution interleaving; counting the first output data subjected to convolution interleaving through a second counter and a third counter to obtain a second count value; and separately generating a second write branch address and a second read branch address according to the second count value to obtain second output data subjected to de-interleaving. The convolution interleaving without redundant data output is matched with the convolution de-interleaving without redundant data input, and the convolution de-interleaving without redundant data input is matched with the convolution interleaving without redundant data output. The throughput rate of the system is improved, and thetime delay of the system is reduced through the convolution de-interleaving without the redundant data input.
Description
technical field [0001] The invention belongs to the field of digital signal transmission, in particular to a method and system for implementing convolution interleaving and deinterleaving FPGA without redundant data. Background technique [0002] In modern digital communication systems, transmission channels are often affected by various interferences and attenuations, so errors in transmitted signals may occur. To this end, channel coding and interleaving are generally used to improve system performance. Channel coding often uses a forward error correction code (FEC, Forward Error Correction) as an outer code, and uses an interleaving code as an inner code. For random errors, it can generally be corrected by channel error correction coding, but for burst errors, interleaving technology must be added. That is, at the transmitting end, the order of the data to be transmitted is disrupted through interleaving, and then at the receiving end, the original order of the data is ...
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