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Processor and interrupt controller therein

A technology for processing interrupts and controllers. It is used in program control design, electrical digital data processing, instruments, etc. It can solve problems such as high-priority interrupt deadlocks, and achieve the effect of improving processing speed and efficient and flexible interrupt processing methods.

Pending Publication Date: 2020-10-09
ALIBABA GRP HLDG LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In addition, when a low-priority interrupt is preempted by a high-priority interrupt, if the low-priority interrupt does not release other resources required by the high-priority interrupt, the high-priority interrupt will also be interrupted. A "deadlock" situation in which execution cannot continue requires the processor to be able to efficiently handle various interrupts with different priorities

Method used

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  • Processor and interrupt controller therein
  • Processor and interrupt controller therein
  • Processor and interrupt controller therein

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Embodiment Construction

[0025] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0026] figure 1 A schematic diagram of a processor 100 according to one embodiment of the present invention is shown. Such as figure 1 As shown, processing system 190 includes processor 100 and various interrupt sources 210 coupled to processor 100 . The interrupt source 210 generates various types of interrupts and is processed by the processor 100 . The processor 100 includes a processor core 150 and an interrupt controller 20...

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Abstract

An interrupt controller in a processor includes: an interrupt sampling unit adapted to receive respective interrupts from respective interrupt sources coupled to the interrupt controller; and an arbitration unit adapted to select an interrupt to be responded from the received respective interrupts. The arbitration unit comprises a selection module suitable for selecting the highest priority interrupt with the highest priority from various interrupts; and a threshold comparison module which is coupled to the selection module and is suitable for comparing the priority of the highest priority interruption with a preset priority threshold. The arbitration unit is suitable for selecting the interrupt with the highest priority as the interrupt to be responded when the threshold comparison moduledetermines that the priority of the interrupt with the highest priority is higher than the priority threshold. The invention further discloses a processor and a system-on-chip comprising the interrupt controller.

Description

technical field [0001] The invention relates to the field of processors, in particular to the field of interrupt processing in the processor. Background technique [0002] The processor needs to handle interrupts from sources such as I / O devices and timers. The processor handles interrupts by executing an interrupt service routine. Since the processor needs to handle different interrupts from multiple interrupt sources, each interrupt has its corresponding interrupt priority and interrupt vector number. Interrupts with high interrupt priority need to be processed first, and it is also expected that interrupts that have been waiting for a long time can be processed immediately so as not to occupy processor resources for too long. Therefore, when the processor processes multiple interrupts, How to efficiently handle various interrupts with different priorities is one of the problems in the processor field. [0003] In addition, when a low-priority interrupt is preempted by ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/26
CPCG06F13/26G06F13/4031G06F9/4818G06F9/485G06F9/30101
Inventor 赵朝君项晓燕陈晨朱涛涛
Owner ALIBABA GRP HLDG LTD
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