Bit line manufacturing method of 3D memory device

Abstract

The present application discloses a bit line manufacturing method of a 3D storage device. The manufacturing method includes: sequentially forming a conductive layer and a first mask stack on the interlayer insulating layer, the conductive layer is in contact with the conductive channel in the interlayer insulating layer; using a spacer process on the conductive layer forming a first hard mask; transferring a pattern of the first hard mask into the conductive layer to form a bit line, wherein the bit line is connected to the channel pillar of the 3D memory device via the conductive channel electrical connection. The manufacturing method can form dense bit lines with small width and small spacing, and the width of the bit lines is basically unchanged along the depth direction extending downward, thereby improving the reading and writing speed and reliability of the 3D storage device.

Description

technical field [0001] The present invention relates to memory technology, and more specifically, to a bit line manufacturing method of a 3D memory device. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] In a 3D memory device with a NAND structure, a semiconductor substrate is used to form a CMOS circuit, and a gate stack structure and multiple channel columns passing through the...

AI Technical Summary

Problems solved by technology

However, the interlayer insulating layer of low-K material introduces a new problem, the breakdown voltage of the 3D memory device decreases with the decrease of the dielectric constant K of the interlayer insulating layer, resulting in poor reliability of the 3D memory device

When the thickness of the interlayer insulating layer is less than 7 nanometers, it is difficult to meet the requirement of a breakdown voltage of 8.5V or more

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