Package stack structure and method for fabricating same

Abstract

A package stack structure and a method for fabricating the same are provided. An electronic component is disposed on the topmost one of a plurality of organic material substrates, and no chip is disposed on the remaining organic material substrates. A predefined layer number of circuit layers are disposed in the organic material substrates, and distributes the thermal stress via the organic material substrates. Therefore, the bottommost one of the organic material substrates will not be separated from a circuit board due to CTE mismatch.

Description

technical field [0001] The present invention relates to a packaging process, in particular to a packaging stack structure and its manufacturing method. Background technique [0002] With the vigorous development of portable electronic products in recent years, all kinds of related products are gradually developing towards the trend of high density, high performance and light, thin, short and small. [0003] Such as figure 1 As shown in , it is a schematic cross-sectional view of a conventional electronic device 1 . The electronic device 1 includes a motherboard 1b such as a circuit board and an electronic package 1a installed on the motherboard 1b. The electronic package 1 a includes a package substrate 11 , a semiconductor chip 10 flip-chip bonded to the package substrate 11 by a plurality of conductive bumps 100 , and a primer 12 fixing the semiconductor chip 10 and covering the conductive bumps 100 . The package substrate 11 of the electronic package 1a is connected to...

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Problems solved by technology

[0005] However, in the existing electronic device 1, the CTE of the plate material of the motherboard 1b does not match the size of the packaging substrate 11, resulting in phase separation between the packaging substrate 11 and the motherboard 1b due to CTE mismatch. Furthermore, there is a problem of connection reliability (Reliability) of the solder balls 13, which causes the packaging substrate 11 to be unable to be effectively electrically connected to the motherboard 1b (such as an open circuit) or fail to pass the reliability test (such as not fully bonded), resulting in the failure of the product. poor yield

[0006] In addition, because the size of the packaging substrate 11 will increase according to the increase in the number of chips required, and the number of layers will become higher and higher, so the process yield of the packaging substrate 11 will also decrease accordingly (that is, the more the number of layers , the greater the error), thus resulting in a sharp increase in the manufacturing cost of the packaging substrate 11

For example, taking the encapsulation substrate 11 of ten circuit layers as an example, the production yield of each circuit layer is about 95%, and the yield rate of the encapsulation substrate 11 of ten circuit layers is 59.8% (ie 0.95%). 10 ), it is difficult to complete the production of the packaging substrate 11 with the existing manufacturing process, and it may be necessary to re-plan the manufacturing process, thus greatly increasing the difficulty of the manufacturing process

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