Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

DVFS-based optimal reconfiguration algorithm

A reconfiguration and algorithm technology, applied in computing, computers, computer components, etc., can solve problems such as unreliability, achieve the effects of improving reliability, reducing overhead, and maximizing stability

Pending Publication Date: 2020-10-30
SHANGHAI TECH UNIV
View PDF5 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The object of the invention is: solve the unreliable problem under the FPGA high radiation environment based on SRAM

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • DVFS-based optimal reconfiguration algorithm

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the teachings of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

[0034] Such as figure 1 As shown, an optimized reconfiguration algorithm based on DVFS provided by the present invention includes the following steps:

[0035] Step 1: First extract the user task information mapped to all user tasks in the FPGA system, where the user task information of the i-th user task includes the running period T of the user task i , The maximum operating frequency of user tasks f i .

[0036] For the i-th user ta...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a DVFS-based optimal reconfiguration algorithm, and the main contribution of the method provided by the invention is as follows: the DVFS-based reconfiguration method can schedule user tasks according to the degree of parallelism of the user tasks so as to allow reconfiguration of more parallel user tasks, thereby achieving higher reliability. According to the heuristic approximation algorithm based on K-Means, the delay of a reconfiguration scheduling algorithm based on DVFS can be reduced to the maximum extent. The invention discloses a method based on K-Means. According to the method, the memory overhead caused by application of DVFS-based reconfiguration scheduling can be reduced. According to the method provided by the invention, the reliability of the FPGA system is improved, and the expenditure of the hardware circuit area is reduced to the maximum extent.

Description

Technical field [0001] The invention relates to a DVFS-based circuit reconfiguration task scheduling method. Background technique [0002] The Field Programmable Gate Array (FPGA) based on Static RAM (SRAM) is the preferred energy-efficient computing platform for applications such as satellites and smart cars. It has powerful computing power and ultra-high performance, and has the flexibility of reconfigurable circuits. At the same time, FPGA has the obvious advantages of low cost and fast time to market compared to dedicated chip ASIC. But SRAM-based FPGAs were not originally designed and developed for high-reliability scenarios. When FPGAs are in a high-intensity radiation environment such as space, they will suffer from single event upset (SEU). In this case, because charged particles hit the chip, the chip’s configuration memory (Configuration Memory) and on-chip memory (BRAM, Flip -flop) can be flipped (R. Santos, S. Venkataraman, A. Das, and A. Kumar, "Criticality-aware ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06F30/39G06K9/62
CPCG06F15/7807G06F15/7871G06F30/39G06F18/23213Y02D10/00G06F30/34G06F2119/06G06F30/3323G06F30/337
Inventor 李睿哈亚军
Owner SHANGHAI TECH UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com