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Semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problem that the planar process and manufacturing technology cannot meet the growing and changing needs of semiconductor devices, etc. The effect of improving performance, simplifying process, reducing cost

Active Publication Date: 2021-07-16
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] With the continuous reduction of the feature size of semiconductor devices and the continuous increase of storage capacity, planar technology and manufacturing technology can no longer meet the growing and changing needs of semiconductor devices

Method used

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  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof

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Embodiment Construction

[0032] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0033] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.

[0034] As indicated in this application and claims, the terms "a", "an", "an" and / or "the" do not refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms "comprising" and "comprising" only suggest the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also contain other st...

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Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a first structure and a second structure, a first bonding layer is formed on the first structure, and the first bonding layer includes The first conductive part on the upper surface of the layer, the second bonding layer is formed on the second structure, and the second bonding layer includes the second conductive part exposed on the upper surface of the second bonding layer; the first conductive part is formed on the first conductive part A conductive bump, and / or, forming a second conductive bump on the second conductive part; and bonding the first structure and the second structure, so that the upper surface of the first bonding layer and the upper surface of the second bonding layer The surfaces contact each other and align the first conductive site with the second conductive site. The present invention can overcome the problem of uneven bonding surfaces between wafers, has the advantages of hybrid bonding and 2.5D packaging through-silicon via interconnection technology, and is conducive to further improving the integration of semiconductor devices and improving the performance of semiconductor devices , and simplify the process and reduce the cost.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure with a hybrid bonding structure and a manufacturing method thereof. Background technique [0002] With the continuous reduction of the feature size of semiconductor devices and the continuous increase of storage capacity, the planar process and manufacturing technology can no longer meet the growing and changing requirements of semiconductor devices. Three-dimensional (3D) device architectures can address density limitations in some planar semiconductor devices. [0003] In order to achieve a three-dimensional architecture, semiconductor wafers (wafers) or dies (die) can be stacked, and the stacked layers can be connected using, for example, through-silicon vias (TSV, Through Silicon Via) or copper-copper (Cu-Cu). Interconnected along the direction of the stack, so as to obtain a smaller footprint, and can reduce the power of the device. [0004] Semicond...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/065H01L23/48H01L23/498H01L23/538H01L21/48H01L21/52H01L23/488H01L27/11551
CPCH01L25/0657H01L23/481H01L23/49816H01L23/49827H01L23/5384H01L24/04H01L24/03H01L24/14H01L24/11H01L21/4853H01L21/52H01L2225/06548H01L2225/0652H01L2224/02H01L2224/03H01L2224/10H01L2224/11H10B41/20H01L2224/16225H01L2924/15311
Inventor 刘峻
Owner YANGTZE MEMORY TECH CO LTD
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