Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device. A first etching barrier layer is formed on a substrate, the horizontal cross section of the first etching barrier layer is circle-shaped and matched with the shape of the bottom face of a groove formed in follow-up process, and therefore the thickness of an etching barrier pattern on the edge outside the bottom face of the groove is increased. In the process of etching to form the groove, the outer edge of the bottom face of the formed groove can stop at the first etching barrier layer, therefore the problem that the bottom face is uneven due to the fact that etching removing speed near the edge outside the groove is larger than the etching removing speed in the middle is solved, the substrate below the etching barrier layer is prevented from being damaged by etching, the phenomenon of short circuit of the device due to the fact that a super-thick metal layer enters the semiconductor substrate when the super-thick metal layer is formed in a deposition mode can be avoided, the super-thick metal layer which is good in electric connection characteristic can be formed in the follow-up process, and the performance of the semiconductor device can be improved.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method for forming a semiconductor device with an ultra-thick metal layer (UltraThickMetal). Background technique [0002] In the field of integrated circuit manufacturing, ultra-thick metal layers (UltraThickMetal) are widely used in semiconductor device structures with sizes ranging from 90nm to 65nm, and the thickness of the ultra-thick metal layer can reach more than 1000nm. [0003] Figure 1 to Figure 2 It is a structural schematic diagram of a manufacturing method of a semiconductor device in the prior art, such as Figure 1 to Figure 2 As shown, the process of making an ultra-thick metal layer includes: first forming an etching stopper layer 20 and an interlayer dielectric layer 30 on the substrate 10; then forming a patterned photoresist layer 40 on the interlayer dielectric layer 30, and forming The patterned photoresist layer 40 is use...

AI Technical Summary

Problems solved by technology

However, because the depth of the trench 50 is relatively large, the interlayer dielectric layer 30 needs to be etched for a long time, so a large amount of etching by-products (Polymer) generated during the etching process stay in the trench 50, and gather in the middle region at the bottom of the trench 50, slowing down the etching speed of the middle region at the bottom of the trench 50, so that the etching speed at the edge region at the bottom of the trench 50 is greater than the etching speed at the middle region, after a long time of etching , leading to an increasing gap in etching thickness, leading to the formation of such figure 2 In the structure shown, the middle region at the bottom of the trench 50 has not reached the etching thickness, while the edge region at the bottom of the trench 50 has been etched into the substrate 10 below. Since the interface flatness at the bottom of the trench 50 is poor, subsequent The ultra-thick metal layer deposited in the trench 50 is easy to form voids, which affects the electrical connection characteristics of the ultra-thick metal interconnection layer, and even causes etching to penetrate the substrate 10, and the subsequently formed ultra-thick metal layer is deposited into the substrate 10. Lead to serious short circuit of the device, affecting the performance of semiconductor devices

[0004] In order to solve the above problems, the prior art adopts the method of simply increasing the thickness of the etch stop layer. However, excessively increasing the thickness of the etch stop layer 20 will greatly increase the overall dielectric constant of the interlayer dielectric layer 30, thereby affecting the semiconductor device. The dielectric capability also affects the performance of semiconductor devices

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