Semiconductor device and manufacturing method of metal silicide separation structure thereof
A metal silicide, metal silicide layer technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of signal delay, device speed reduction, surface resistance and contact resistance increase, etc.
Pending Publication Date: 2020-11-06
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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[0002] As the integration of semiconductor devices continues to increase, the critical dimensions of semiconductor devices continue to decrease, and many problems have arisen accordingly, such as the corresponding increase in the surface resistance and contact resistance of the active region and gate region of the device, resulting in the corresponding speed of the device decrease, the signal is delayed
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[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.
[0022] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...
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The invention discloses a semiconductor device and a manufacturing method of a metal silicide separation structure thereof. The manufacturing method comprises the steps of providing a semiconductor substrate comprising a first NMOS device region and a PMOS device region; forming a first barrier layer on the PMOS device region to expose the first NMOS device region; forming a first metal silicide layer on the surface of the exposed first NMOS device region; forming a second barrier layer on the first NMOS device region to expose the PMOS device region; and forming a second metal silicide layeron the surface of the exposed PMOS device region. By using the barrier layers twice, the NMOS device region and the PMOS device region are selectively separated, so that metal silicide structures withdifferent surface resistances can be formed on the surfaces of the first NMOS device region and the PMOS device region.
Description
technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a method for manufacturing a metal silicide separation structure thereof. Background technique [0002] As the integration of semiconductor devices continues to increase, the critical dimensions of semiconductor devices continue to decrease, and many problems have arisen accordingly, such as the corresponding increase in the surface resistance and contact resistance of the active region and gate region of the device, resulting in the corresponding speed of the device lower, the signal is delayed. Therefore, an interconnection structure with low resistivity becomes a key element in the manufacture of highly integrated semiconductor devices. [0003] In order to reduce the contact resistance of the device active region and the gate region, the process method of metal silicide is introduced, usually the metal silicide is form...
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IPC IPC(8): H01L27/092H01L21/8238
CPCH01L27/0922H01L21/823892H01L21/823878
Inventor 申靖浩熊文娟蒋浩杰李亭亭罗英
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI