Neural network hardware accelerator

Abstract

The invention discloses a neural network hardware accelerator. An assembly line architecture of the hardware accelerator comprises an instruction obtaining module used for acquiring instructions an instruction decoding module used for performing instruction decoding operation; a semi-precision floating point operation module used for carrying out one-dimensional vector operation; an activation function calculation module used for calculating an activation function in a table lookup mode; a floating point post-processing unit used for performing floating point operation on the data calculated by the activation function; and a caching module used for caching intermediate data in the neural network algorithm implementation process. Register files which are distributed on an assembly line andlocated on the same level as the instruction decoding module are used for temporarily storing related instructions, data and addresses in the neural network algorithm implementation process. The hardware resource utilization rate of the hardware accelerator in the RNN neural network algorithm implementation process can be greatly improved, so that the unit power consumption efficiency of the RNN neural network algorithm with the unit calculation amount in unit time when the RNN neural network algorithm is operated through the hardware accelerator is improved.

Description

technical field [0001] The present application relates to the technical field of artificial intelligence, in particular to a neural network hardware accelerator. Background technique [0002] At present, hardware accelerators for neural networks include Google's TPU, NVDIA's NVDLA, Cambrian and so on. The mainstream neural network hardware accelerator has done a lot of calculation optimization for the CNN (Convolutional Neural Networks, Convolutional Neural Network) network, and in the process of hardware calculation, it has done convolution operations for convolution and convolution kernels of different sizes. Targeted optimization. [0003] It can be seen that the current architecture of the entire neural network hardware accelerator is biased towards CNN optimization, and this part is indeed the part that requires the most computing power in the neural network algorithm. Although these neural network hardware accelerators can also be used for RNN (ie, Recurrent Neural N...

AI Technical Summary

Problems solved by technology

Although these neural network hardware accelerators can also be used for RNN (ie, Recurrent Neural Network, cyclic neural network) neural networks, there are few calculation optimizations for RNN neural networks, and the calculation efficiency ratio is too poor

That is to say, if the same existing hardware is used to calculate CNN, there will be little waste of resources, but if it is used to calculate RNN, there will be a lot of waste of resources.

More waste of resources means lower power consumption and computing power. In this way, the architecture of neural network hardware accelerators has no advantages in terms of power consumption efficiency and cost.

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