DDR3 controller based on DFI standard

Abstract

Disclosed is a DDR3 controller based on a DFI standard comprising a request analysis interface module, a grouping and ID marking module, a Bank read-write management module, a read-write data channelmodule, a first-level queue cache module, an instruction sending module, a non-read-write module and a DFI interface module. The invention ensures high efficiency of rate transmission by regulated grouping, command taking and re-sequencing principles. By setting a group command quantity threshold, a command request time period is labelled and combined with a reordering strategy to prevent commandaging; reading and writing of the same bank address are carried out according to a request sequence through a grouping principle, related ID attributes are defined to achieve one-to-one correspondenceof commands and data, and transmission reliability is jointly achieved.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a DDR3 controller based on the DFI standard. Background technique [0002] Through the analysis of the DDR3 protocol standard, the main two aspects that can affect the efficiency of DDR3 are: 1. Frequent switching between reading and writing, which increases the bandwidth waste of switching time between reading and writing; 2. Frequent different rows of the same bank The switching of the bank increases the pre-charging and activation time and also causes bandwidth waste; therefore, the design of the controller should try to ensure long-term continuous reading or continuous writing operations, and try to avoid the switching interval between different rows of the same bank; currently on the market The mainstream DDR controller is mainly the official Xilinx MIG soft core, but the Xilinx MIG core does not consider the mechanism of preventing command aging, and cannot guarantee th...

AI Technical Summary

Problems solved by technology

[0002] Through the analysis of the DDR3 protocol standard, the main two aspects that can affect the efficiency of DDR3 are: 1. Frequent switching between reading and writing, which increases the bandwidth waste of switching time between reading and writing; 2. Frequent different rows of the same bank The switching of the bank increases the pre-charging and activation time and also causes bandwidth waste; therefore, the design of the controller should try to ensure long-term continuous reading or continuous writing operations, and try to avoid the switching interval between different rows of the same bank; currently on the market The mainstream DDR controller is mainly the official Xilinx MIG soft core, but the Xilinx MIG core does not consider the mechanism of preventing command aging, and cannot guarantee the timely response of commands during the reordering strategy process, which will cause the commands to continue to age and cause the commands to hang; Many controllers cannot achieve both reliability and efficiency. While maximizing the bandwidth, it will cause the aging of the request, which will cause unexpected consequences.

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