Chip packaging structure

Abstract

The invention discloses a chip packaging structure. The packaging structure comprises a substrate, a chip, a first metal enclosing wall, a second metal enclosing wall, pins and an insulating packagingbody, the substrate is provided with a first surface, a second surface, via holes, a first conductive pattern and a second conductive pattern. The first conductive pattern is located in the peripheral area of the first surface. The second conductive pattern is located on the second surface. The via holes are filled with electroplating metal and penetrate through the first surface and the second surface; the chip is located in intermediate region, the first metal enclosing wall is arranged on the first conductive pattern; the second metal enclosing wall covers the upper surface of the first metal enclosing wall; the lower surface area of the second metal enclosing wall is smaller than the upper surface area of the first metal enclosing wall, the part, not covered by the second metal enclosing wall, of the upper surface of the first metal enclosing wall is a bonding wire area, one end of the pin is connected with the chip, the other end of the pin is connected with the bonding wire area, and the insulating packaging body is coupled to the second metal enclosing wall. Therefore, the overall size of the chip packaging structure can be reduced, and the packaging cost can be saved.

Description

technical field [0001] The invention relates to a chip packaging structure, in particular to a chip packaging structure with metal walls. Background technique [0002] The chip packaging structure currently on the market is a chip packaging structure with a reflective cup-shaped package body, and the bonding wire area for connecting gold wires is arranged in the functional area inside the reflective cup. As a result, the following problems exist: as the size of the chip increases, according to the above design, the functional area must be enlarged accordingly, and the package body must also be enlarged accordingly. The size of the final chip package structure is too large, which is not conducive to installation, circuit design. [0003] In addition, when the chip operates at high power and the temperature rises, the pressure difference between the inside and outside of the airtight package will cause the gas in the package to heat up, thereby destroying the package. [000...

AI Technical Summary

Problems solved by technology

As a result, the following problems exist: as the size of the chip increases, according to the above design, the functional area must be enlarged accordingly, and the package body must also be enlarged accordingly. The size of the final chip package structure is too large, which is not conducive to installation, circuit design

[0003] In addition, when the chip operates at high power and the temperature rises, the pressure difference between the inside and outside of the airtight package will cause the gas in the package to heat up, thereby destroying the package.

Images