Directory controller test excitation generation method based on genetic algorithm

Abstract

The invention discloses a directory controller test excitation generation method based on a genetic algorithm. The directory controller test excitation generation method comprises the steps of S1, performing symbol coding of the genetic algorithm for test characteristics of a directory controller; S2, creating a primary population of test excitation, and selecting random chromosomes to add into the population based on a negative selection algorithm; S3, performing mutation operation to generate new chromosomes, and adding the new chromosomes into the population based on the negative selectionalgorithm; S4, performing crossover operation to generate new chromosomes, and adding the new chromosomes into the population based on the negative selection algorithm; and S5, repeating the step S3S4until the maximum genetic algebra is reached or chromosomes with fitness values greater than or equal to a set threshold appear. The relationship between the coverage rate and excitation input can bemined, generation of random test excitation is guided, new chromosomes are supervised and selected to be added into the population according to a negative selection algorithm, the least redundant test excitation is achieved, different coverage rate function points are covered as soon as possible, the test time is shortened, and the verification efficiency is improved.

Description

technical field [0001] The invention relates to chip design technology, in particular to a genetic algorithm-based method for generating test incentives for a directory controller. Background technique [0002] On-chip multi-core processors (CMP, Chip Multi-processors) have become the direction of processor development. With the increasing demand for data communication between multi-core and multi-thread, on-chip integrated large-capacity Cache (high-speed buffer) realizes data sharing and interaction, thereby Reduce memory access latency and reduce access conflicts. Such as figure 1 A 64-core processor as shown adopts a CMP structure, including a processor core (core), a Cache, a network on chip (Network on Chip, NoC), a directory controller (Directory Control Unit, DCU), a storage controller ( Memory Control Unit). figure 1 Among them, Core is the CPU core, which completes the scheduling and execution of instructions; Cache is a high-speed cache, and two cores share a C...

AI Technical Summary

Problems solved by technology

Writing test vectors manually takes a lot of time and labor costs, and sometimes it is difficult to meet the large number of test vectors with wide coverage required by regression testing; random test vectors, the size and length of the generated test vectors are flexible and controllable, but

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