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Memory device with bit line noise suppressing scheme

A noise suppression and memory technology, applied in the field of integrated circuits and bit line noise suppression solutions, can solve problems such as multiple noises

Pending Publication Date: 2021-02-09
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Capacitive coupling can cause excessive noise during data read operations and becomes increasingly problematic as integration levels increase

Method used

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  • Memory device with bit line noise suppressing scheme
  • Memory device with bit line noise suppressing scheme
  • Memory device with bit line noise suppressing scheme

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0016] Some embodiments include integrated memory with noise suppression structures below the bit lines. Noise suppression structures can be configured to reduce problematic parasitic capacitance that can be associated with bit lines. The noise suppression structure can be electrically connected to the bit line and can also be electrically connected to the sense amplifier circuit. The sense amplifier circuit may also be coupled to a control circuit, such as a data read / write circuit, which may be composed of CMOS (complementary metal oxide semiconductor) circuits. refer to Figures 1 to 10 Example embodiments are described.

[0017] refer to figure 1 , illustrating the areas of the integrated memory 10 . The memory includes bit lines BL-Aa, BL-Ab, BL-Ba, BL-Bb, BL-Ca, and BL-Cb; which may be referred to as first, second, third, fourth, fifth, respectively and the sixth digit line.

[0018] The bit lines are in a pair relationship. Specifically, bit lines BL-Aa and BL-Ab...

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PUM

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Abstract

The invention relates to a memory device with a bit line noise suppression scheme. Some embodiments include an integrated memory having a first bitline coupled with a first set of memory cells, and having a second bitline coupled with a second set of memory cells. The first and second bitlines are comparatively coupled through a sense amplifier. A first noise suppression line is adjacent to a region of the first bitline and extends parallel to the region of the first bitline. The first noise suppression line is electrically connected with one of the first and second bitlines and not with the other of the first and second bitlines. A second noise suppression line is adjacent to a region of the second bitline and extends parallel to the region of the second bitline. The second noise suppression line is electrically connected with the other of the first and second bitlines.

Description

technical field [0001] The present invention relates to integrated circuits; such as memory arrays, for example. The present invention relates to bit line noise suppression schemes for integrated memories. Background technique [0002] Highly integrated memories have closely spaced memory cells and bit lines. Unwanted capacitive coupling between closely spaced bit lines can be problematic. Capacitive coupling may arise from both inter-pair coupling between adjacent bit line pairs and intra-pair coupling within bit line pairs (e.g. H. Hidaka et al. Twisted Bit-Line Architectures for Multi-Megabit DRAM's"; IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, February 1989; pages 21 to 27). Capacitive coupling can cause excessive noise during data read operations and becomes increasingly problematic as integration levels increase. It is desirable to develop new architectures that reduce or eliminate problematic capacitive coupling. Contents of the invention [0003] On...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/12G11C7/18G11C7/06G11C7/08H10B12/00
CPCG11C7/12G11C7/18G11C7/062G11C7/08G11C11/4097G11C11/4091G11C7/02G11C11/4094H01L23/5222H01L25/18H10B12/50H01L23/528H01L23/58H10B12/30
Inventor 祐川光成C·J·卡瓦姆拉
Owner MICRON TECH INC