Neural network processing-oriented data output circuit structure scheduled according to priorities

Abstract

The invention belongs to the field of integrated circuit design, and particularly relates to a neural network processing-oriented data output circuit structure scheduled according to priorities, whichmainly structurally comprises four parts: an X-bus unit module for determining the data transmission priority of a horizontal arithmetic unit; a Y-bus unit module used for determining the data transmission priority of a vertical arithmetic unit; a suffix configuration unit module used for parameter filling; and an address calculation unit module used for interacting with the storage unit. The circuit adopts a two-stage bus form, data transmission priorities are set on two-stage buses in advance, and data congestion and bus idleness are avoided while the data transmission sequence is standardized. Meanwhile, in order to improve the data reusability and the data memory access efficiency, an address calculation unit better serving four-dimensional address calculation is designed, and orderlywrite-back of data is guaranteed through an internal historical information table. According to the invention, the output result transmission efficiency in neural network processing can be effectively improved.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to a data output circuit structure oriented to neural network processing and scheduled according to priority. Background technique [0002] Neural network algorithms have been well applied in important fields such as computer vision, speech recognition, and robot control. However, various applications have continuously put forward higher requirements for the accuracy and complexity of neural network algorithms, leading to a series of challenges in the implementation of the algorithms. sexual issues. The recent research on neural network processor architecture shows that the array-based parallel spatial processor architecture, with a fixed data flow strategy, and with a specific data transmission path, can make good use of the high parallelism and internal nature of the neural network algorithm itself. High multiplexing, which greatly reduces the number of data a...

AI Technical Summary

Problems solved by technology

For data competition, it is possible to pre-set data transmission priorities for all computing units, traverse all computing units in one cycle or multiple cycles, and write back intermediate results according to priority settings. However, as the array size increases, Large, the clock delay of this direct traversal will be very large

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