3D memory device and manufacturing method thereof

Abstract

The present application discloses a 3D memory device and a method for manufacturing the same. The memory device includes a substrate; a stacked structure on the substrate, the stacked structure includes a plurality of gate conductors and a plurality of interlayer insulating layers stacked alternately ; a channel hole penetrating the stack structure; a channel structure located in the channel hole and a filling layer covering the channel structure; wherein, the filling layer is formed by multiple depositions, and is formed after multiple depositions Gas etching is performed between deposition processes, so that the top of the cavity in the filling layer is located below the uppermost interlayer insulating layer in the stacked structure, so as to further reduce the size of the cavity in the filling layer and reduce the seam at the top of the cavity The height of the 3D memory device increases the thickness of the filling layer above the seam, so as to meet the subsequent processing requirements and improve the yield and reliability of the 3D memory device.

Description

technical field [0001] The present invention relates to memory technology, and more particularly, to 3D memory devices and manufacturing methods thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectively. Compared w...

AI Technical Summary

Problems solved by technology

However, in the prior art, in order to increase the storage capacity, the number of stacked layers in the stacked structure is increasing, resulting in an increase in thickness, which in turn causes an increase in the aspect ratio of the channel column, so that the filling layer fills the channel column When the core is affected, a seam will be generated at a higher position during the filling process, so that an unfilled airtight cavity will be formed under the seam, affecting product performance

The higher the aspect ratio of the channel column, the larger the cavity, and the more obvious its impact on device performance, and the seam at the higher position of the channel column will also affect the setting and arrangement of the structure above the channel column , the seam may be etched and penetrated in the subsequent processing steps, which cannot meet the subsequent processing requirements

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