Three-dimensional memory and manufacturing method thereof

A manufacturing method and memory technology, applied in the field of memory, can solve problems such as deformation and fracture of gate lines and grooves, affecting the performance of 3D NAND memory, etc., and achieve the effect of improving performance

Active Publication Date: 2021-03-09
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the existing 3D NAND memory uses gate line separation grooves (or gate separation structures) to separate blocks. Due to the stress of the step regi

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  • Three-dimensional memory and manufacturing method thereof

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Embodiment Construction

[0033] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. In particular, the following examples are only used to illustrate the present invention, but not to limit the scope of the present invention. Likewise, the following embodiments are only some of the embodiments of the present invention but not all of them. All other embodiments obtained by those skilled in the art without creative efforts all fall within the protection scope of the present invention.

[0034] In addition, the directional terms mentioned in the present invention, such as [top], [bottom], [front], [back], [left], [right], [inside], [outside], [side], etc., only is the direction with reference to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention. In the various figures, structurally similar elements are denoted by the sa...

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Abstract

The invention relates to a three-dimensional memory and a manufacturing method thereof. The three-dimensional memory comprises a substrate, a gate stacking structure, a virtual separation structure, and agate separation structure, wherein the gate stacking structure is located on the substrate and is divided into a core region and a step region which are sequentially arranged along a first transverse direction parallel to the substrate; the virtual separation structure is perpendicular to the substrate and penetrates through the step region in the first transverse direction so as to divide thestep region into a plurality of block step regions; the gate separation structure is perpendicular to the substrate and penetrates the core region in a first lateral direction on an imaginary extension line of the virtual separation structure to divide the core region into a plurality of block core regions, the gate separation structure has a first side end portion in contact with the virtual separation structure in the first lateral direction, the virtual separation structure has a second side end portion in contact with the gate separation structure in a first lateral direction, the first side end portion is enclosed within the second side end portion, or the second side end portion is enclosed within the first side end portion. Therefore, the problem that the gate separation structureis easy to deform and even break in the step region when the gate separation structure is used for separating the step region is avoided.

Description

【Technical field】 [0001] The invention relates to the technical field of memory, in particular to a three-dimensional memory and a manufacturing method thereof. 【Background technique】 [0002] As technology develops, the semiconductor industry is constantly looking for new production methods to allow each memory die in a memory device to have a greater number of memory cells. Among them, 3D NAND (three-dimensional NAND) memory has become a cutting-edge three-dimensional memory technology with great development potential due to its advantages of high storage density and low cost. [0003] 3D NAND memory usually includes one or more slice memory areas. At least one side of the chip storage area is usually provided with a stepped area for pulling out the gate. The step area has a stepped shape. Slice storage areas and terrace areas are usually split into multiple blocks to obtain multiple block storage areas. [0004] However, the existing 3D NAND memory uses gate line sepa...

Claims

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Application Information

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IPC IPC(8): H01L27/11565H01L27/1157H01L27/11582
CPCH10B43/10H10B43/50H10B43/35H10B43/27
Inventor 许宗珂袁彬张强威许波
Owner YANGTZE MEMORY TECH CO LTD
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