PLC system and method for achieving LVDS communication based on FPGA

Abstract

The embodiment of the invention discloses a PLC system and method for realizing LVDS (Low Voltage Differential Signaling) communication based on an FPGA. The PLC system comprises a main control moduleand at least one expansion module; the main control module comprises an MCU and an FPGA main control chip, the MCU is connected with the FPGA main control chip, and the FPGA main control chip is connected with the expansion module through an LVDS interface; the FPGA main control chip controls the expansion module through a data frame, and the expansion module responds to the control of the FPGA main control chip through the data frame. According to the embodiment of the invention, hardware facilities of the PLC processor can be reduced, and the structure is optimized, so that the cost is reduced, and the operation efficiency is improved.

Description

technical field [0001] The invention relates to the field of industrial automatic control, in particular to a PLC system and a method for realizing LVDS communication based on FPGA. Background technique [0002] PLC (Programmable Logic Controller) is an electronic system for digital operations, often used in the fields of industry, aviation, and weapon equipment control. It uses a programmable memory to store and execute logic operations, sequence control, timing, Instructions for operations such as counting and arithmetic operations are used to control various types of mechanical equipment or production processes through digital or analog input and output. [0003] In the existing PLC, usually a plurality of extended I / Os connected to it are controlled by the PLC host to realize different functions. In the existing technology, the connection between the PLC host and multiple extended I / Os is relatively complicated. For example, the PLC host includes a processor, a serial d...

AI Technical Summary

Problems solved by technology

In the existing technology, the connection between the PLC host and multiple extended I / Os is relatively complicated. For example, the PLC host includes a processor, a serial deserializer chip, a phase-locked loop chip, an FPGA, and inter-board connections. In addition, in the extended I / O, the last extended I / O needs to set the end terminal to facilitate the PLC to identify multiple extended I / Os. The last extended I / O in / O, not only increases the cost, but also brings inconvenience to the user

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