IP core for satellite-borne SRAM type FPGA configuration and refresh control

Abstract

The invention discloses an IP core for satellite-borne SRAM type FPGA configuration and refresh control, which is used for reading an FPGA configuration file under the control of an external processorand carrying out on-orbit configuration and refresh control on one or more FPGAs, and comprises a configuration file reading and state output module, a data storage analysis module, an enabling control module and a configuration refresh top layer module, the configuration file reading and state output module is used for reading an FPGA configuration file, receiving a processor instruction and outputting a refreshing state of FPGAs; the data storage and analysis module is used for reading the FPGA configuration file, decoding the FPGA configuration file and sending the decoded FPGA configuration file to the configuration refreshing top layer module; the enabling control module is used for generating a configuration enabling signal and a refresh enabling signal and sending the configurationenabling signal and the refresh enabling signal to the configuration refresh top layer module; and the configuration refresh top layer module is used for generating a configuration control command and a refresh control command, sending the configuration control command and the refresh control command to the specified FPGAs, and reading the refresh state of the FPGAs.

Description

technical field [0001] The invention relates to the technical field of aviation and aerospace electronics integration, in particular to an IP core for on-board SRAM FPGA configuration and refresh control. Background technique [0002] Due to its diversity and repeatability in functional configuration, flexibility and efficiency in massive data processing, FPGA is widely used in spacecraft electronic systems, and undertakes tasks such as digital signal processing and image processing in space environments. Xilinx's SRAM-type Virtex series FPGAs have more advantages in performance and capacity, and can be reconfigured according to different functional requirements. [0003] However, the FPGA of the SRAM process is greatly affected by space radiation. The logic state of the internal configuration memory is often flipped due to the impact of high-energy particles (single event flip), which may lead to loss of spacecraft information or functional interruption. Due to the partic...

AI Technical Summary

Problems solved by technology

[0011] In the prior art, there is a problem of poor scalability in SRAM FPGA configuration and refresh. The purpose of the present invention is to overcome the above-mentioned defects in the prior art, and provide an IP core for on-board SRAM FPGA configuration and refresh control, which has scalability and Features of strong portability

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