Large-scale complex layout resistance extraction acceleration method

Abstract

The invention discloses a large-scale complex layout resistance extraction acceleration method. The method comprises the following steps of: segmenting a complex graph into a plurality of simple sub-graphs; storing the simple sub-graph data into a quick graph query data structure; matching the complex graphs associated with all the simple sub-graphs with the corresponding port graphs; and calculating parasitic resistances from all ports to the ports. According to the large-scale complex layout resistance extraction acceleration method, a complex graph can be segmented into a plurality of simple sub-graphs, each port graph (or blocking graph) can quickly inquire the sub-graphs with a connection relationship, and the graph geometric operation efficiency of the port graphs (or blocking graphs) and the simple sub-graphs is very high; the matching relationship between the port pattern and the resistor pattern can be quickly found, so that the resistance extraction time is greatly shortened,the efficiency is improved, the matching correctness of the port and the resistor pattern is ensured, and the port-to-port parasitic resistance extraction accuracy is ensured.

Description

technical field [0001] The invention relates to the technical field of automatic design of semiconductor integrated circuits, in particular to the post-simulation of semiconductor circuits and the extraction technology of layout parasitic resistance. Background technique [0002] In integrated circuit design and display panel design, it is necessary to perform electrical (or optical) simulation on the designed circuit to judge whether the circuit design is up to standard. In circuit simulation, it is necessary to consider the influence of parasitic effects on the circuit timing in the semiconductor process. Usually, it is necessary to extract parasitic resistance from the layout of the integrated circuit and add it to the simulation circuit netlist for timing verification. The extraction of parasitic resistance in EDA software needs to process the input layout to obtain the actual two-dimensional graphics of the required extracted resistance port to port and the attributes o...

AI Technical Summary

Problems solved by technology

When extracting parasitic resistance, it is necessary to match the extracted graphics and the corresponding port graphics (or blocking graphics). As the scale of integrated circuits continues to increase, the layout graphics are becoming more and more complex. The number of corresponding port graphics (or blocking graphics) More and more, the time of matching graphics has obviously affected the time efficiency of resistance extraction

[0003] In the extraction of parasitic resistance of complex integrated circuits, if the extracted signal line layout graphics are very complex (such as power supply signal line graphics in power circuits, current path signal line graphics in flat panel display circuits), layout is performed according to the netlist resistance port node information After cutting, the matching efficiency of the corresponding resistance pattern and the port pattern (or blocking pattern) is low, which will cause considerable time overhead. In addition, it takes too long to calculate the port-to-port resistance by using methods such as finite element methods, and the overall parasitic resistance extraction time is too long

[0004] If the large-scale complex graph is not segmented, it is necessary to use the complex graph to query all port graphs (or block graphs), and perform graph intersection operations with the queried port graphs (or block graphs) that may be connected. Due to the number of complex graph vertices It is huge, and the efficiency of graphic geometric calculation is very low, resulting in a long time for graphic matching

Images