An Accelerated Method for Resistor Extraction in Large-Scale and Complex Layout

Abstract

A large-scale complex layout resistance extraction acceleration method, comprising the following steps: cutting the complex graph into a plurality of simple sub-graphs; storing the simple sub-graph data into a fast graph query data structure; matching all the simple sub-graph associations The complex graph of the corresponding port graph; calculates all port-to-port parasitic resistances. The large-scale complex layout resistance extraction acceleration method of the present invention can divide a complex graph into multiple simple sub-graphs, and each port graph (or block graph) can quickly query sub-graphs with connections, which are different from simple sub-graphs. The efficiency of graphic geometric calculation is very high, and the matching relationship between port graphics and resistor graphics can be quickly found, which greatly shortens the resistance extraction time, improves efficiency, and also ensures the correctness of matching between ports and resistor graphics, ensuring port-to-port parasitic resistance Extraction accuracy.

Description

technical field [0001] The invention relates to the technical field of automatic design of semiconductor integrated circuits, in particular to the post-simulation and layout parasitic resistance extraction technology of semiconductor circuits. Background technique [0002] In integrated circuit design and display panel design, it is necessary to perform electrical (or optical) simulation on the designed circuit to judge whether the circuit design meets the standard. During circuit simulation, it is necessary to consider the influence of parasitic effects in the semiconductor process on circuit timing. Usually, it is necessary to extract parasitic resistances from the layout of the integrated circuit and add them to the simulated circuit netlist for timing verification. The parasitic resistance extraction in EDA software needs to process the input layout, and obtain the actual two-dimensional graphics of the extracted resistance port to the port and the properties of the port...

AI Technical Summary

Problems solved by technology

When extracting parasitic resistance, it is necessary to match the extracted graphics and the corresponding port graphics (or blocking graphics). As the scale of integrated circuits continues to increase, the layout graphics are becoming more and more complex. The number of corresponding port graphics (or blocking graphics) More and more, the time of matching graphics has obviously affected the time efficiency of resistance extraction

[0003] In the extraction of parasitic resistance of complex integrated circuits, if the extracted signal line layout graphics are very complex (such as power supply signal line graphics in power circuits, current path signal line graphics in flat panel display circuits), layout is performed according to the netlist resistance port node information After cutting, the matching efficiency of the corresponding resistance pattern and the port pattern (or blocking pattern) is low, which will cause considerable time overhead. In addition, it takes too long to calculate the port-to-port resistance by using methods such as finite element methods, and the overall parasitic resistance extraction time is too long

[0004] If the large-scale complex graph is not segmented, it is necessary to use the complex graph to query all port graphs (or block graphs), and perform graph intersection operations with the queried port graphs (or block graphs) that may be connected. Due to the number of complex graph vertices It is huge, and the efficiency of graphic geometric calculation is very low, resulting in a long time for graphic matching

Images