Three-dimensional memory structure and preparation method thereof

Abstract

The invention provides a three-dimensional memory structure and a preparation method thereof. The three-dimensional memory structure comprises a semiconductor layer, a bottom selection gate stack structure, a dielectric supporting structure, a storage gate stacking structure and a grid line gap, wherein thesemiconductor layer comprises a core region, a step region and a peripheral region which are sequentially arranged along a first direction; the bottom selection gate stack structure is formed on the semiconductor layer; the dielectric supporting structure is located in the step region, and the dielectric supporting structure sequentially penetrates through the bottom selection gate stack structure and the semiconductor layer; the storage gate stacking structure is formed on the bottom selection gate stack structure; and the grid line gap extends along the first direction, and the grid line gap sequentially penetrates through the storage grid stack structure and the bottom selection grid stack structure and extends into the semiconductor layer. By utilizing the structure, the dielectric supporting structure is not damaged when the semiconductor sacrificial layer is removed based on grid line gap etching, the dielectric supporting structure plays a supporting role, and the collapse phenomenon in the etching process of the three-dimensional memory structure is improved.

Description

technical field [0001] The invention belongs to the field of semiconductor design and manufacture, and in particular relates to a three-dimensional memory structure and a preparation method thereof. Background technique [0002] The semiconductor substrate of the three-dimensional memory has a stacked structure, and the vertical channel structure is located in the stacked structure and runs through the stacked structure. When the stacked structure (including stacked silicon nitride and oxide films) is deposited on the semiconductor substrate, the semiconductor A sacrificial polysilicon layer is introduced between the substrate and the stacked structure. After the gate line gap is etched, it is necessary to deposit various protective films in the gate line gap and perform multiple etchings. Then, based on the gate line gap, the sacrificial polysilicon layer and the The functional sidewall of the vertical channel structure surrounding the position of the sacrificial polysilico...

AI Technical Summary

Problems solved by technology

In this process, since the dummy channel hole in the step region is filled with silicon oxide, when the ONO structure at the bottom of the vertical channel structure in the core region is removed, the silicon oxide in the dummy channel hole in the step region will also were removed together, causing problems with step supports in the step area

[0003] In addition, in the three-dimensional memory based on back selection, metal contacts and peripheral conductive pillars connected to metal contacts are prone to direct contact with highly doped polysilicon at the bottom, which will affect the reliability of the device

Images