High-reliability NMOS array structure and preparation method thereof
An array structure and reliability technology, applied in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., can solve the problems of NMOS source-drain breakdown voltage reduction, P-well concentration cannot be increased, and restrict low-voltage NMOS, etc., to improve work The effect of improving reliability and power consumption tolerance
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Embodiment 1
[0025] High reliability NMOS array structure
[0026] like figure 1 As shown, a P well region 2 is arranged above the P-type substrate 1, a plurality of P+ implantation diffusion regions are arranged at intervals on the upper part of the P well region 2, and a plurality of N+ implantation diffusion regions are arranged between two adjacent P+ implantation diffusion regions, Between the N+ implanted diffusion regions and the lower part of the N+ implanted diffusion regions are communicated through the P well region. In this embodiment, three P+ implantation diffusion regions are spaced at the upper part of the P well region 2 , namely, the first P+ implantation diffusion region 3 , the second P+ implantation diffusion region 4 , and the third P+ implantation diffusion region 5 . A PB layer and / or a ZP layer is disposed below the P+ implantation diffusion region, and both ends of the PB layer and / or the ZP layer are aligned with the ends of the P+ implantation diffusion region ...
Embodiment 2
[0032] High reliability NMOS array structure
[0033] The first P+ implantation diffusion region 3, the second P+ implantation diffusion region 4, and the third P+ implantation diffusion region 5 are all provided with a PB layer 17 for lateral double diffusion MOS transistors or a ZP layer 18 for Zener transistors. The PB layer 17 or the ZP layer 18 is reasonably selected according to the consideration of the devices used in the product and the cost. For example, only NMOS arrays and lateral double-diffused MOS transistors are used in the product, but no voltage regulators are used. At the same time, the cost control requirements are very strict, and the reliability requirements of NMOS arrays are not very high, so only the PB layer 17 can be used instead of the ZP layer. 18. In this way, additional lithography times will not be added, so that the reliability can be partially improved on the premise that the tape-out cost is not increased. Similarly, if the product only uses...
Embodiment 3
[0039] Preparation method of high reliability NMOS array structure
[0040] A layer of P well region is covered on the P-type substrate; a plurality of P+ implantation diffusion regions are formed at intervals on the upper part of the P well region, and a PB layer or ZP layer is formed under the P+ implantation diffusion region; the plurality of P+ implantation diffusion regions are formed The region synchronous processing operation is completed, that is, multiple P+ windows are etched simultaneously in the upper part of the P well region, and the implantation and annealing of P-type impurities are simultaneously performed in each P+ window, thus forming multiple P+ implantation diffusions at the same time. Area.
[0041] A plurality of N+ implantation diffusion regions are formed between two adjacent P+ implantation diffusion regions, and the simultaneous processing operation of the plurality of N+ implantation diffusion regions is completed, that is, between two adjacent P+ ...
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