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Wafer detection method

A detection method and wafer technology, applied in the direction of semiconductor/solid-state device testing/measurement, can solve problems such as disadvantages, improve process yield, etc., and achieve the effect of improving yield

Active Publication Date: 2021-04-16
XIA TAI XIN SEMICON QING DAO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this sampling method will cause the position of the measured point on the wafer to be fixed all the time, while other points to be measured have not been measured, which is not conducive to improving the process yield.

Method used

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Experimental program
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no. 1 approach

[0034] see figure 1 , the first embodiment of the present invention provides a wafer detection method, including the following steps:

[0035] Step S11, please also refer to figure 2 , providing N 0 Wafers 1 to be tested, each wafer 1 to be tested includes N 1 10 testable locations.

[0036] For example, the number of wafers 1 to be tested is 20 (ie N 0 =20). Each wafer 1 to be tested includes 160 testable positions 10 (ie N 1 =160).

[0037] Step S12, please also refer to image 3 , divide each wafer 1 to be tested into a plurality of sampling areas according to a predetermined division method, the plurality of sampling areas are correspondingly set in different wafers 1 to be tested, and the sampling areas correspondingly set in different wafers 1 to be tested are Regions form a set of sampling regions.

[0038] As shown in the figure, each wafer 1 to be tested may include three sampling areas, respectively marked as a first sampling area 20a, a second sampling are...

no. 2 approach

[0059] see Figure 7 , the second embodiment of the present invention also provides a wafer detection method, including the following steps:

[0060] Step S71, please also refer to figure 2 , providing N 0 Wafers 1 to be tested, each wafer 1 to be tested includes N 1 10 testable locations.

[0061] For example, the number of wafers 1 to be tested is 40 (ie N 0 = 40). Each wafer 1 to be tested includes 160 testable positions 10 (ie N 1 =160).

[0062] Step S72, please refer to image 3 , divide each wafer 1 to be tested into a plurality of sampling areas according to a predetermined division method, the plurality of sampling areas are correspondingly set in different wafers 1 to be tested, and the sampling areas correspondingly set in different wafers 1 to be tested are Regions form a set of sampling regions.

[0063] As shown in the figure, each wafer 1 to be tested may include three sampling areas, respectively marked as a first sampling area 20a, a second sampling ...

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Abstract

The invention discloses a wafer detection method, which comprises the steps: providing N0 to-be-detected wafers, wherein each to-be-detected wafer comprise N1 testable positions; dividing each to-be-detected wafer into a plurality of sampling areas according to a predetermined division mode, wherein the plurality of sampling areas are respectively and correspondingly arranged in different to-be-detected wafers, and the sampling areas correspondingly arranged in different to-be-detected wafers form a group of sampling areas; determining the number of the sampling positions of each sampling area in one to-be-detected wafer, wherein the sampling positions of all the to-be-detected wafers are in one-to-one correspondence with the N1 testable positions, the number of the sampling positions of each to-be-detected wafer is N2, and N1=N0*N2; and according to the number of the sampling positions of each sampling area, selecting the sampling positions in each sampling area of the to-be-detected wafer in sequence for testing, wherein the sampling positions selected by the same group of sampling areas in different to-be-detected wafers are different from one another.

Description

technical field [0001] The invention relates to a wafer detection method. Background technique [0002] In the semiconductor manufacturing process, it is necessary to measure parameters such as the critical dimension of the pattern on the wafer, the offset of the pattern, or the thickness of the film layer to ensure the process yield or quality. The critical dimension of the pattern on the wafer is usually measured by a critical dimension scanning electron microscope (Critical Dimension Scanning Electron Microscope). Due to the limitation of the measurement time and the number of machines, it is usually impossible to measure all the chip positions in each wafer. are measured, but are measured by sampling. [0003] For example, there are 68 exposure fields (shots) that need to be exposed on a wafer in the yellow light process, each exposure field contains 4 chip areas, and each chip area contains a point to be measured, so there are 272 shots in a wafer point to be tested. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66
Inventor 李其衡刘智龙
Owner XIA TAI XIN SEMICON QING DAO LTD
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