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Semiconductor memory device

A semiconductor and memory technology, applied in the field of three-dimensional semiconductor memory devices, can solve problems such as limitations

Pending Publication Date: 2021-04-30
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, although the integration density of 2D semiconductor devices continues to increase, it is still limited because more expensive equipment is required to form finer patterns.

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0021] figure 1 is a schematic circuit diagram illustrating a cell array of a semiconductor memory device according to some example embodiments of inventive concepts.

[0022] refer to figure 1 In other words, a memory cell array of a semiconductor memory device according to some example embodiments of inventive concepts may include a plurality of sub-cell arrays SCA. The sub-unit array SCA may be arranged along the second direction D2.

[0023] Each sub-cell array SCA may include a plurality of bit lines BL, a plurality of word lines WL, and / or a plurality of memory cell transistors MCT. Each memory cell transistor MCT may be connected between a corresponding one of the word lines WL and a corresponding one of the bit lines BL.

[0024] The bit line BL may be a conductive pattern (eg, a metal line) vertically spaced apart from the substrate. The bit line BL may extend in the first direction D1. The bit lines BL in each subcell array SCA may be spaced apart from each othe...

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PUM

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Abstract

A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2019-0134616 filed on October 28, 2019 at the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] Example embodiments of inventive concepts relate to a semiconductor memory device, and more particularly, to a three-dimensional (3D) semiconductor memory device having improved integration density. Background technique [0003] Semiconductor devices have become highly integrated to provide improved performance and / or lower manufacturing costs. The integration density of semiconductor devices affects the cost of semiconductor devices, resulting in a demand for more highly integrated semiconductor devices. The integration density of a typical two-dimensional (2D) or planar semiconductor device can be mainly determined by the area occupied by a unit memory cell. Therefore, the integration density of a typical 2D semic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H01L21/8242
CPCH10B12/30H10B12/02G11C11/4097H01L28/86H10B12/03H10B12/05H10B12/482H01L27/0688H10B12/48
Inventor 金哉勳朴光浩孙龙勳宋炫知李耕希郑承宰
Owner SAMSUNG ELECTRONICS CO LTD
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