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Fast-converging bit-flipping decoder for low-density parity-check codes

A parity-check matrix and decoder technology, applied in the field of non-volatile memory devices, can solve problems such as unreliability of multi-layer NAND flash memory devices

Pending Publication Date: 2021-05-11
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, multi-layer NAND flash memory devices can be inherently unreliable and often require the use of ECC to significantly improve data reliability, but at the expense of additional storage space for ECC parity bits

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  • Fast-converging bit-flipping decoder for low-density parity-check codes
  • Fast-converging bit-flipping decoder for low-density parity-check codes
  • Fast-converging bit-flipping decoder for low-density parity-check codes

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Embodiment Construction

[0019] Low density parity check (LDPC) codes are an important part of linear block error correction codes (ECC) and have been widely used in data storage systems. LDPC codes can be decoded using two classes of decoding algorithms: soft information message passing algorithms such as minimum sum or sum product algorithms, and hard decision algorithms such as bit flipping algorithms. Soft information decoding algorithms provide good decoding performance, but require a lot of computational resources. Therefore, they exhibit high complexity in hardware implementation. In contrast, hardware implementations of hard-decision decoders exhibit low complexity and reduced latency requirements due to simple computational units and smaller connection networks, and have been developed to provide similar error correction performance. In other systems, a combination of hard decoding and soft decoding implementations is employed.

[0020] In most bit-flipping decoder architectures, the correc...

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Abstract

Disclosed are devices, systems and methods improving the convergence of a bit-flipping decoder in a non-volatile memory device. An example method includes: receiving a noisy codeword, the codeword having been generated based on a parity check matrix of a low-density parity-check code and provided to a communication channel prior to reception by the bit-flipping decoder, and performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages. In some embodiments, performing a single decoding iteration includes: computing a metric corresponding to a single column of the parity check matrix, flipping at least one bit in the single column upon a determination that the metric exceeds a flipping threshold, computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and updating the flipping threshold upon a determination that the syndrome is not zero.

Description

technical field [0001] This application document relates generally to non-volatile memory devices, and more particularly, to error correction in non-volatile memory devices. Background technique [0002] For any data storage device and data transfer, data integrity is an important feature. Strong error correction codes (ECC) are recommended for various types of data storage devices including NAND flash memory devices. [0003] Solid state drives (SSDs) utilize multiple layers of NAND flash memory devices for persistent storage. However, multi-layer NAND flash memory devices can be inherently unreliable and often require the use of ECC to significantly improve data reliability, but at the expense of additional storage space for ECC parity bits. Therefore, there is a need for ECC that can provide data protection with improved convergence properties. SUMMARY OF THE INVENTION [0004] Embodiments of the disclosed technology relate to a method, apparatus, and system for impr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10
CPCG06F11/1032H03M13/1108G06F11/1068H04L1/0051
Inventor 张帆熊晨荣王浩博段宏伟夏江南
Owner SK HYNIX INC