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Fast converging soft bit-flipping decoder for low-density parity check codes

A parity check matrix and decoder technology, applied in the field of non-volatile memory devices, can solve problems such as unreliability of multi-layer NAND flash memory devices

Pending Publication Date: 2021-05-28
SK HYNIX INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, multi-layer NAND flash devices can be inherently unreliable and often require the use of ECC to significantly improve data reliability, but at the expense of additional storage space for ECC parity bits

Method used

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  • Fast converging soft bit-flipping decoder for low-density parity check codes
  • Fast converging soft bit-flipping decoder for low-density parity check codes
  • Fast converging soft bit-flipping decoder for low-density parity check codes

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Embodiment Construction

[0016] Low-density parity-check (LDPC) codes are an important part of linear block error-correcting codes (ECC), and have been widely used in data storage systems. LDPC codes can be decoded using two classes of decoding algorithms: soft information message passing algorithms such as minimum-sum or sum-product algorithms, and hard-decision algorithms such as bit-flip algorithms. Soft information decoding algorithms provide good decoding performance, but require a lot of computing resources. Therefore, they exhibit high complexity in hardware implementation. In contrast, hardware implementations of hard-decision decoders show low complexity and reduced latency requirements due to simple computational units and smaller connection networks, and have been developed to provide comparable error correction performance. In other systems, a combination of hard and soft decoding implementations are employed.

[0017] In most bit-flip decoder architectures, the correction capability of ...

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Abstract

The present disclosure relates to a fast convergence soft bit-flipping decoder for low density parity check codes, and a device, system, and method for improving convergence of a soft bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy code word, the code word having been generated based on a parity check matrix of an LDPC code and provided to a communication channel prior to reception by the soft bit-flipping decoder, generating, based on the noisy code word, one or more messages for passing between a plurality of variable nodes and a plurality of check nodes of the soft bit-flipping decoder, generating a reliability metric for each of the one or more messages, storing the reliability metric only for messages comprising magnitudes that are less than or equal to a predetermined threshold value; and performing, based on the one or more messages and the associated reliability metric for at least one of the one more messages, a single decoding iteration of the soft bit-flipping decoder.

Description

technical field [0001] This document relates generally to non-volatile memory devices and, more particularly, to error correction in non-volatile memory devices. Background technique [0002] Data integrity is an important feature of any data storage device and data transmission. Strong error correction codes (ECC) are recommended for various types of data storage devices including NAND flash memory devices. [0003] Solid state drives (SSDs) utilize multi-layer NAND flash memory devices for persistent storage. However, multi-layer NAND flash memory devices can be inherently unreliable and often require the use of ECC to significantly improve data reliability, but at the expense of additional storage space for ECC parity bits. Therefore, there is a need for ECC that can provide data protection with improved convergence properties. Contents of the invention [0004] Embodiments of the disclosed technology relate to methods, apparatus, and systems for improving the conver...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10
CPCG06F11/1032H03M13/1108G06F11/1012H03M13/1111H03M13/255H03M13/6331
Inventor 美萨姆·阿沙迪张帆王浩博段宏伟
Owner SK HYNIX INC