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Data layout conscious processing in memory architecture for executing neural network model

A neural network model and memory technology, applied in the field of non-transitory computer-readable storage media, can solve the problems of large amount of calculation and memory occupation

Pending Publication Date: 2021-06-04
ALIBABA GRP HLDG LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As neural network models, especially deep neural network (DNN) models, become large and complex, with hundreds of layers and millions of weights, executing a neural network model is not only computationally intensive, but also memory-intensive
Because a conventional von Neumann architecture has separate processing units and storage units, when a neural network model is processed on a conventional von Neumann architecture, a large amount of data occurs between the processing unit and the storage unit transmission, which becomes the bottleneck for processing neural network models

Method used

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  • Data layout conscious processing in memory architecture for executing neural network model
  • Data layout conscious processing in memory architecture for executing neural network model
  • Data layout conscious processing in memory architecture for executing neural network model

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Embodiment Construction

[0021] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein like numerals in different drawings indicate the same or similar elements unless otherwise indicated. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with aspects of the invention as set forth in the appended claims.

[0022] figure 1 An exemplary processing-in-memory (PIM) block configuration consistent with embodiments of the present disclosure is shown. The PIM block 100 includes a memory cell array 110 , a block controller 120 , a block row driver 131 and a block column driver 132 . Although some embodiments will be shown using ReRAM (Resistive Random Access Memory) as an example, it sho...

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Abstract

The present disclosure relates to a device supporting in-memory processing (PIM) for executing a neural network model. The device supporting PIM comprises a storage block component, and the storage block component comprises a first storage block array; a second memory block array adjacent to the first memory block array; and a plurality of first data links associated with the first memory block array and the second memory block array, wherein each data link of the plurality of first data links is communicatively connected to two respective memory blocks from the first memory block array and the second memory block array, respectively; and a second data link communicatively connected to the plurality of first data links, the data from the first memory block of the first memory block array being transmittable to the second memory block of the second memory block array via the plurality of first data links and the second data link.

Description

Background technique [0001] Machine learning has been widely used in various fields such as natural language processing, speech recognition, image classification, etc. In machine learning, neural network models are constantly proliferating and becoming more complex. As neural network models, especially deep neural network (DNN) models, become large and complex, with hundreds of layers and millions of weights, executing a neural network model is not only computationally intensive, but also memory-intensive. Because a conventional von Neumann architecture has separate processing units and storage units, when a neural network model is processed on a conventional von Neumann architecture, a large amount of data occurs between the processing unit and the storage unit transmission, which becomes the bottleneck for processing neural network models. [0002] Processing In Memory (PIM) technology, which enables calculations to be performed in storage units, has emerged to address suc...

Claims

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Application Information

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IPC IPC(8): G06N3/063
CPCG06N3/063G11C11/54G11C8/12G11C13/0023G06N3/084G06N3/065G11C16/10G06N3/04G06F15/7821
Inventor 周铭轩张伟丰陈国洋
Owner ALIBABA GRP HLDG LTD