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Wafer size packaging structure and manufacturing method thereof

A technology of size packaging and chip, applied in the field of packaging structure, can solve the problems of skew, shrinkage and interference of semiconductor chips, and achieve the effect of avoiding electromagnetic wave interference and avoiding chip skew

Pending Publication Date: 2021-06-04
PAN JIT INT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The first object of the present invention is to provide a chip size packaging structure that can solve the problems of semiconductor chip skew and electromagnetic wave interference and reduce the overall appearance size

Method used

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  • Wafer size packaging structure and manufacturing method thereof
  • Wafer size packaging structure and manufacturing method thereof
  • Wafer size packaging structure and manufacturing method thereof

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Embodiment Construction

[0029] refer to figure 2 , a first embodiment of the chip size package structure of the present invention includes a base 2 , a semiconductor element 3 , and an electrical insulator 4 .

[0030] The base 2 includes a first plane 24, a second plane 25 opposite to the first plane 24, and a concave surface that is recessed from the first plane 24 toward the second plane 25 and defines a filling space 20 26, and the first plane 24, the concave surface 26 and the second plane 25 are electrically connected to each other.

[0031] The semiconductor element 3 is disposed in the filling space 20 so as to be surrounded by the concave surface 26 of the base 2, and includes a wafer 30 and a first electrode 31 and a second electrode 32 oppositely disposed on the wafer 30, And the second electrode 32 is electrically connected to the concave surface 26 of the base 2 .

[0032] The electrical insulator 4 is filled in the filling space 20 to cover the concave surface 26 of the base 2 and th...

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PUM

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Abstract

A wafer scale packaging structure includes a base, a semiconductor device and an electrical insulator. The base comprises a first plane, a second plane opposite to the first plane and a concave surface which is recessed from the first plane to the second plane and defines a filling space, and the first plane, the concave surface and the second plane are electrically conducted with each other. The semiconductor element is arranged in the filling space to be surrounded by the concave surface of the base and comprises a wafer, a first electrode and a second electrode, the first electrode and the second electrode are oppositely arranged on the wafer, and the second electrode is electrically connected with the concave surface of the base. The electrical insulator is filled in the filling space to cover the concave surface of the base and the semiconductor element and expose the first electrode. A lead frame of a cantilever structure does not need to be used, and the second electrode of the semiconductor element is electrically conducted to the first plane through the concave surface and does not need to be hot-pressed to the lead frame of the cantilever structure through welding flux, so the wafer can be prevented from skewing and external electromagnetic wave interference can be avoided. The invention further provides a manufacturing method of the wafer size packaging structure.

Description

technical field [0001] The present invention relates to a package structure, in particular to a chip scale package (CSP for short) structure and a manufacturing method thereof. Background technique [0002] General semiconductor components such as diodes or transistors are mostly carried by lead frames, and the electrodes in the semiconductor components are electrically connected to the lead frames by wire bonding, and then A packaging structure is formed by encapsulating semiconductor elements, bonding wires and lead frames with encapsulant to partially expose the lead frames. The packaging structure uses bonding wires to connect the electrical signals generated by the semiconductor elements to the lead frame exposed outside the packaging glue, so as to transmit the electrical signals to the outside through the lead frame exposed outside the packaging glue. In addition, the current industry can also see such as figure 1 As shown, it is a package structure formed by omitti...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/552H01L21/50H01L21/56
CPCH01L23/3114H01L23/552H01L21/50H01L21/56H01L2224/18
Inventor 何中雄
Owner PAN JIT INT