[0022] Next, the technical solutions in the present application embodiment will be described in the present application, and the described embodiments are intended, and the described embodiments are merely embodiments, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative labor premises, all of the present application protected.
[0023] It should be noted that all techniques and scientific terms used herein are the same meaning in the art, unless otherwise defined. The terms used herein in the specification of the present application are merely intended to describe specific embodiments, and is not to limit the present application.
[0024] Such as Figure 1-2 As shown, a storage system based on the NVME protocol controls the SATA disk, including the processor and the FPGA module, the processor and the FPGA module are connected by the PCIe bus, and the processor is mounted, and the FPGA module mounts a second memory and SATA storage arrays, SATA storage arrays include multiple SATA disks, where:
[0025] The processor is used to send read-write instructions to the FPGA module and manage data in the SATA storage array. The read-write instruction is NVME protocol instruction. When the write instruction, the processor receives the first data through the first external interface, and The write instruction and the first data are issued to the first memory, and the FPGA module receives the second data by the second external interface, and the second data is issued to the second memory; when the read command, the processor will read the instruction and Data in the SATA storage array is issued to the first memory, and the data in the first memory is transmitted through the first external interface. The FPGA module issues data in the SATA storage array to the second memory and passes the second external interface. Data in the second memory is sent to the outside;
[0026] The FPGA module is used to obtain read and write instructions in the first memory and parse the read-write instruction to the SATA protocol instruction, and control the data interaction between the SATA storage array and the first memory or second memory according to the SATA protocol instruction;
[0027] The first memory is used to cache the data read from the SATA storage array;
[0028] Second Memory, used to cache data read from the SATA storage array;
[0029] SATA storage array for storing first data and second data.
[0030] Where the SATA disk is controlled by the FPGA module and reads and writes. Under the control of the FPGA module, the first memory, the second memory is interactive between the SATA storage array, and realizes the storage system to continuously high bandwidth. Read and write. The processor is equipped with a file system to manage data in the SATA storage array in the form of a standard file system to facilitate use. At the same time, the processor can get the number, initialization status, and capacity information of the SATA disk.
[0031] The storage system uses NVME protocol to control SATA storage arrays, greatly optimizes software design and data flow, so that the SATA disk has a higher read and write speed than a pure SATA protocol storage system, and uses FPGA high-speed parallel characteristics to make storage systems to meet high performance demand, continuous The read and write performance is not less than 6.4GB / s, high storage performance, good compatibility, easy to use. Avoid using SATA system-related components, greatly reducing power consumption and hardware costs. At the same time, the SATA disk is used as a storage body, retains the SATA power consumption, the operating temperature range is wide, and the working temperature can be stabilized at -55 ° C ~ + 70 ° C, and it is advantageous for the board miniaturization. Easy to implement a PCIe interface implementation controls multiple SATA disks, solving problems with current processors support SATA interface.
[0032] In an embodiment, the processor is an embedded processor.
[0033] Among them, the embedded processor has a higher operating stability, smaller power consumption, strong environment, good integration, and is suitable for security confidentiality.
[0034] In an embodiment, the FPGA module includes a protocol conversion module for implementing the NVME protocol to the SATA protocol and the RAID module configured for multiple SATA disk parallel read, and the protocol conversion module is connected to the RAID module, the RAID module and each SATA. Dish connection.
[0035] Such as figure 2 As shown, the protocol conversion module can convert the read-and-write instructions issued by the processor to the SATA protocol instruction to implement the SATA storage array using the NVME protocol, so that the read and write speed of the SATA disk is higher than the pure SATA protocol storage system. , Software design is simpler. The RAID module is a prior art for writing to multiple SATA disk pane reads over, achieving autonomous control, including a variety of different levels, such as RAID0, RAID1, RAID5, RAID10, RAID50, etc., respectively, can provide different speeds, security, respectively. And cost performance, the appropriate RAID level can be selected based on the actual situation to meet the requirements of the user's availability, performance, and capacity of storage systems.
[0036] In an embodiment, the FPGA module also includes a decryption module, a protocol conversion module, and a plus decryption module is sequentially connected to the RAID module, which is used to decrypt data in the SATA storage array.
[0037]Among them, the FPGA module is provided with a decryption module, such as when the write command is written under the processor, the NVME protocol instruction is resorial after the FPGA module is restructured into SATA protocol instructions. The data stream is common in FPGA interface, which can add the decryption module to add decryption to the data by the FPGA module, and then perform SATA storage array read and write, further improve security, system flexibility, and avoid processing NVME Agreement or SATA protocol, improve operational efficiency.
[0038] The workflow of the storage system is as follows:
[0039] The process of writing an external data to the SATA storage array:
[0040] 1) The FPGA module receives the second data and burst the second data into the second memory, and the data in the second memory is written to the SATA storage array through the FPGA module.
[0041] Specifically, the processor invokes the FPGA module to start recording through a character device (such as a keyboard, mouse, etc.), that is, the FPGA module starts from the second external interface, such as a high-speed serial interface, receives the second data and handled the first The two data is cached in the second memory. After the cache is completed, the FPGA module reports the interrupt signal notification processor, the processor receives the interrupt signal after writing the file, the write address is the second memory. Under the processor, the command is written to the first memory. The write instruction is NVME protocol instruction. After obtaining the write instruction in the first memory, the FPGA module is parsed to the SATA protocol instruction, and transported from the second memory according to the source address information in the SATA protocol instruction. Data, according to the target address information in the SATA protocol instruction stores the data in the second memory of the transport into the sector of the specified SATA storage array, the storage is completed, the FPGA module returns the completion information to the processor, the processor check completion information. After the end of the operation.
[0042] 2) The processor receives the first data and causing the first data into the first memory, inform the FPGA module to write data in the first memory into the SATA storage array.
[0043] Specifically, the processor receives the first data (such as network data, etc.) through the first external interface, and caching the first data into the first memory. After the cache is completed, the interrupt signal is reported to notify the processor, the processor receives the interrupt signal after writing File, write address is the address of the first memory. The processor sends a write instruction to the FPGA module, and the write instruction is NVME protocol instruction. The FPGA module obtains the write instruction in the first memory to the SATA protocol instruction, and according to the source address information in the SATA protocol instruction, the first memory data, according to the target address information in the SATA protocol instruction, will be transported in the first memory in accordance with the target address information in the SATA protocol instruction. The data is stored in the sector specified in the SATA storage array. After the storage is complete, the FPGA module returns the completion information to the processor, the processor checks the completion information, ends the operation.
[0044] The data in the SATA storage array reads to the outside:
[0045] 1) The processor controls the FPGA module to read the data in the SATA storage array to the second memory, and the FPGA module then sends data in the second memory to the second external interface of the FPGA module.
[0046] Specifically, the processor calls the FPGA module's drive module through a character device (such as a keyboard, mouse, etc.) to notify the FPGA module to start playback requests. The processor is read to the first memory, and the read command is NVME protocol instruction. After obtaining the read instruction in the first memory, the FPGA module is parsed to the SATA protocol instruction, and according to the SATA storage array according to the source address information in the SATA protocol instruction. Handling data, according to the target address information in the SATA protocol instruction stores the data in the SATA storage array of the transport into the second memory, the data in the second memory is sent through the second external interface of the FPGA module, and generates an interrupt signal notification processor. Complete data read.
[0047] 2) The processor controls the FPGA module to read the data in the SATA storage array to the first memory, and send data in the first memory through the processor's first external interface.
[0048] Specifically, the processor is read to the first memory, and the read command is NVME protocol instruction, and the FPGA module obtains the read instruction in the first memory to resolve the SATA protocol instruction, and according to the source address information in the SATA protocol instruction from SATA. In the memory of the array, the data in accordance with the target address information in the SATA protocol instruction stores the data in the SATA storage array of the transport into the first memory, and the data in the first memory passes through the processor's first external interface (such as network interface, etc.). Send to an external device, such as the peer PC, etc., and report the interrupt signal notification processor after the write is completed.
[0049] Further, when power-on, the processor loads the drive module of the FPGA module, initializes the FPGA module, and creates admin queues and IO queues in the FPGA module according to the read and write instructions of the processor:
[0050] The processor initializes the NVME register of the FPGA module and configures AQA, ASQ, and ACQ.
[0051] Admin Queue: Update the FPGA module DB ring in the first memory, then refresh the SQ0TDBL; the FPGA module detects that the SQ0TDBL value changes, initiates admin_sq information to the first memory; the FPGA module receives the feedback data, parse the data content, complete The identify command, the CREATE IO SQ command, the CREATE IO CQ command, that is, the physical address of IO SQ and IO CQ; updates admin_cq, and upload the interrupt signal notification processor This time is complete.
[0052] IO queue: Update the FPGA module DB ring in the first memory, then refresh SQ1TDBL; the FPGA module detects that the SQ1TDBL value changes, and the first memory initiates IO_SQ information; after receiving the feedback data, the FPGA module analyzes the data content, complete DMA reads the DMA write operation, that is, implementing the interaction of the first memory data and SATA data; updating IO_CQ, and uploading the interrupt signal notification processor This processing is completed.
[0053] DMA read: Extract the read address of the first memory data in IO_SQ information, SADR, SATA disk write address DADR and data length LEN; the FPGA module reads the data amount of the data length LEN to the first memory data, according to 4KB data The quantitative wheel is transferred to each SATA disk; the SATA disk automatically writes the received data to the SATA disk address DADR to complete the DMA read operation.
[0054] DMA Write: Extract the write address DADR, SATA disk read address SADR, and data length LEN; the FPGA module is sent to each SATA disk; SATA disk is automatically read from the SATA disk address SADR Take the amount of data length LEN, and synthesize the received data in a 4 kb rotation, then write the synthesized data to the write address DADR position of the first memory data, thereby completing the DMA write operation.
[0055] The various techniques of the above embodiments can be arbitrarily combined, in order to make the description, the possible combinations of various technical features in the above embodiments are not described, however, as long as the combination of these technical features does not have contradictions, it should It is considered to be the scope of this specification.
[0056] The above embodiments only express the specific and detailed embodiments of the present application, but it is not understood to limit the limitation of the patent scope of the present application. It should be noted that in terms of one of ordinary skill in the art, several deformations and improvements can be made without departing from the context of this application, which belongs to the scope of the present application. Therefore, the scope of protection of the patent according to the present application should be taken as the appended claims.
