Low-cost zero-delay SAR-ADC hardware correction algorithm
A technology of correction algorithm and hardware algorithm, which is applied in the field of SAR-ADC, can solve the problems of clock occupation and large resource consumption, and achieve the effects of simplified correction, low consumption and simple calculation method
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[0015] A low-cost zero-delay SAR-ADC hardware correction algorithm adopts the following processing steps:
[0016] S1, define register AM and register AK, configure a hardware arithmetic circuit by register AM and register AK, the sign bit of register AM is Fm, the sign bit of register AK is Fk, and hardware algorithm circuit is input with ADC output data Ya;
[0017] S2, the algorithm circuit obtains the correction value TEMP1 through Ya, wherein
[0018] TEMP1=Ya+(Fm?AM:-AM);
[0019] S3, the algorithm circuit obtains the correction value TEMP2 through TEMP1, wherein
[0020] TEMP2=(Fk?AK:-AK)*TEMP1;
[0021] S4, the algorithm circuit obtains the ADC output data correction value Yb according to the correction value TEMP1 and the correction value TEMP2, wherein
[0022] Yb=TEMP1+TEMP2.
[0023] In the above embodiment, a hardware algorithm circuit is configured through a register, the calculation method is simple, does not need to occupy the sampling time of the ADC, can ...
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