Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Low-cost zero-delay SAR-ADC hardware correction algorithm

A technology of correction algorithm and hardware algorithm, which is applied in the field of SAR-ADC, can solve the problems of clock occupation and large resource consumption, and achieve the effects of simplified correction, low consumption and simple calculation method

Inactive Publication Date: 2021-06-29
深圳前海维晟智能技术有限公司
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, the conventional compensation method is through software compensation. The currently known hardware compensation methods generally have the disadvantages of large resource consumption and clock occupation.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0015] A low-cost zero-delay SAR-ADC hardware correction algorithm adopts the following processing steps:

[0016] S1, define register AM and register AK, configure a hardware arithmetic circuit by register AM and register AK, the sign bit of register AM is Fm, the sign bit of register AK is Fk, and hardware algorithm circuit is input with ADC output data Ya;

[0017] S2, the algorithm circuit obtains the correction value TEMP1 through Ya, wherein

[0018] TEMP1=Ya+(Fm?AM:-AM);

[0019] S3, the algorithm circuit obtains the correction value TEMP2 through TEMP1, wherein

[0020] TEMP2=(Fk?AK:-AK)*TEMP1;

[0021] S4, the algorithm circuit obtains the ADC output data correction value Yb according to the correction value TEMP1 and the correction value TEMP2, wherein

[0022] Yb=TEMP1+TEMP2.

[0023] In the above embodiment, a hardware algorithm circuit is configured through a register, the calculation method is simple, does not need to occupy the sampling time of the ADC, can ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A low-cost zero-delay SAR-ADC hardware correction algorithm adopts the following processing steps that S1, a register AM and a register AK are defined, a hardware algorithm circuit is configured through the register AM and the register AK, the sign bit of the register AM is Fm, the sign bit of the register AK is Fk, and the hardware algorithm circuit takes ADC output data Ya as input; S2, an algorithm circuit obtains correction value TEMP1 through Ya, wherein TEMP1 is shown in the description; S3, the algorithm circuit obtains a correction value TEMP2 through TEMP1, wherein TEMP2 is shown in the description; S4, the algorithm circuit obtains an ADC output data correction value Yb according to the correction value TEMP1 and the correction value TEMP2, wherein Yb = TEMP1 + TEMP2. A hardware algorithm circuit is configured through the register, the calculation method is simple, the sampling time of the ADC does not need to be occupied, the correction of the ADC can be calculated in a simplified mode, and the method has the advantages of being low in consumption and zero in time delay.

Description

technical field [0001] The invention relates to the technical field of SAR-ADC, in particular to a low-cost zero-delay SAR-ADC hardware correction algorithm. Background technique [0002] Successive approximation register analog-to-digital converters (SAR-ADCs) account for most of the medium to high resolution ADC market, with sampling rates up to 5Msps and resolutions from 8 to 18 bits. In view of the fact that the SAR architecture allows high-performance, low-power ADCs to be packaged in small sizes, and has the characteristics of high speed, low cost, and high precision, SAR-ADC is especially suitable for systems with strict size requirements and is widely integrated in MCU chips. . [0003] However, due to the deviation of the production process, the ADC characteristics of each chip will have a little deviation, so correction and compensation are required to obtain better consistency. At present, the conventional compensation method is through software compensation, an...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/10
Inventor 戴锐吴晓勇崔松叶
Owner 深圳前海维晟智能技术有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products