Memory management method and device, electronic device and storage medium

Abstract

The invention relates to a memory management method and device, an electronic device and a storage medium. The memory management method comprises the steps of receiving a memory obtaining request, wherein a large-page memory is used for storing the large-page memory blocks; searching a target large-page memory block matched with the memory acquisition request in the large-page memory, wherein the target large-page memory block is a next large-page memory block to be distributed in the large-page memory; returning the address mapping information of the target large-page memory block in a shared memory corresponding to the large-page memory, and switching the use state of the target large-page memory block to a locking state, wherein the shared memory is used for storing the address mapping information between the large-page memory block in the large-page memory and the address range of the shared memory. According to the embodiment of the invention, a requester of the memory obtaining request can obtain a complete and continuous block of memory through one request, the situation that cross-memory-block access is continuously carried out for several times aiming at one request is avoided, the hit rate of the cpu cache is improved, and the delay of request response is reduced.

Description

technical field [0001] The present application relates to the technical field of computers, and in particular to a memory management method, device, electronic equipment and storage medium. Background technique [0002] Memory Pool is a memory allocation method, also known as fixed-size-blocks allocation. The memory pool is a technology that applies for the allocation of a certain number of memory blocks of equal size (generally) for backup before actually using the memory. When there is a new memory demand, a part of the memory block is allocated from the memory pool, and if the memory block is not enough, continue to apply for new memory. [0003] However, several memories requested by the memory pool may have discontinuous and non-linear addresses, and the several memories may span several memory blocks, which requires the CPU to access memory in different memory blocks several times in succession, while the CPU To access the memory, you need to access the page table fi...

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Problems solved by technology

[0003] However, several memories requested by the memory pool may have discontinuous and non-linear addresses, and the several memories may span several memory blocks, which requires the CPU to access memory in different memory blocks several times in succession, while the CPU To access the memory, you need to access the page table first. When multiple accesses are frequent, the hit rate of the cpu cache decreases, resulting in a very high response delay.

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