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gan device structure and preparation method thereof

A technology of device structure and auxiliary graphics, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of parasitic capacitance and difficult alignment of GaN devices, achieve small parasitic capacitance, reduce parasitic effects, The effect of addressing device limitations

Active Publication Date: 2022-07-19
浙江集迈科微电子有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a GaN device structure and its preparation method, which are used to solve the problems of difficulty in effectively aligning GaN devices and the existence of parasitic capacitance in the prior art.

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  • gan device structure and preparation method thereof
  • gan device structure and preparation method thereof

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Embodiment Construction

[0046] The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention. In addition, the three-dimensional spatial dimensions of length, width and depth should be included i...

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Abstract

The invention provides a GaN device structure and a preparation method. The preparation includes: preparing a source auxiliary pattern and a drain auxiliary pattern on a substrate, forming a gate groove between the two, and defining a gate-source spacing, a gate-drain spacing and a gate length respectively; Preparation of passivation layer; preparation of shielding auxiliary layer and removing part of passivation layer based on it; preparation of source electrode and drain electrode; removal of shielding auxiliary layer to reveal gate trench; preparation of gate electrode structure; removal of source auxiliary pattern and drain auxiliary graphics. The present invention predefines gate length, source-gate and gate-drain spacing by introducing source auxiliary patterns and drain auxiliary patterns, which can be completed in one step, and subsequent steps do not require precise photolithography alignment, with high process feasibility and stability. Simple. The floating gate can be prepared at the same time, so that the parasitic capacitance of the device is small, which is beneficial to small-sized and high-frequency devices. The solution of the present invention solves the yield problem caused by equipment limitations and process alignment errors, and at the same time reduces the parasitic effect of the device to the greatest extent.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a GaN device structure and a preparation method thereof. Background technique [0002] The research and application of GaN materials is currently the frontier and hotspot of global semiconductor research. It is a new type of semiconductor material for the development of microelectronic devices and optoelectronic devices. The third generation of semiconductor materials after semiconductor materials. It has the properties of wide direct band gap, strong atomic bond, high thermal conductivity, good chemical stability (hardly corroded by any acid) and strong radiation resistance. [0003] However, with the development and demand of technology, especially the smaller size of the device, the precision requirements of GaN devices are getting higher and higher. The existing precise alignment process is complicated and the error is large. In additio...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L29/20H01L21/336
CPCH01L29/78H01L29/0603H01L29/0684H01L29/2003H01L29/66477
Inventor 马飞邹鹏辉周康邱士起
Owner 浙江集迈科微电子有限公司
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