A high-performance high-speed input buffer circuit

Abstract

The invention discloses a high-performance high-speed input buffer circuit, which relates to the field of circuit technology. The high-speed input buffer circuit is provided with an output clamping circuit at the differential output end of each differential module, and the differential output ends of two differential modules The output signal is cross-coupled by the cross-coupling circuit and then outputs a pair of differential output signals to the subsequent stage circuit. The output clamp circuit can make the output flip quickly, improve the bandwidth, and stabilize the output common-mode voltage at the same time, while the cross-coupling circuit improves gain, so that the high-speed input buffer circuit meets the dual requirements of bandwidth and gain.

Description

technical field [0001] The invention relates to the technical field of circuits, in particular to a high-performance high-speed input buffer circuit. Background technique [0002] When the signal is input from outside the chip, it needs to be received by the input buffer circuit, and the signal level is converted to the internal voltage domain level of the chip, so that the signal can be further processed. When designing an input buffer circuit, the following aspects need to be considered: [0003] 1. The level standard of the input signal, such as common mode level VCM, differential mode level VID, different level standards often define different VCM and VID ranges, if the input buffer circuit needs to be compatible with multiple level standards, for example Compatible with LVDS / DDR / MIPI applications, the possible VCM is 0.07V~1.8V, and the VID is 0.07V~1.8V. On the one hand, it is necessary to adopt a full-swing input circuit structure to realize the normal operation of ...

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Problems solved by technology

figure 1 The input buffer circuit shown in the existing structure is difficult to meet this requirement

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