Capacitor network mismatch correction method and device, electronic equipment and storage medium

Abstract

The invention discloses a capacitor network mismatch correction method and device, electronic equipment and a storage medium. The method comprises the steps: 1, dividing a plurality of capacitors of a predetermined digital code of a to-be-corrected ADC into a plurality of capacitor banks; 2, combining the plurality of capacitor banks, equally dividing the capacitor banks into first and second part capacitors, connecting a free end of the first part capacitor to a first reference voltage, connecting a free end of the second part capacitor to a second reference voltage, and connecting common ends of the first and second part capacitors to a common mode voltage; 3, disconnecting the common end of the first part capacitor and the second part capacitor from the common-mode voltage, and changing the free end of the first part capacitor and the free end of the second part capacitor to be connected with the common-mode voltage; 4, obtaining the common terminal voltage of each capacitor combination at the step 2 and the step 3, and correcting the capacitor network mismatch of the predetermined digital code according to the voltage difference between the common terminal voltage of each capacitor combination at the step 2 and the step 3; 5, executing the steps 1-4 according to a sequence from high order to low order of each digital code in the ADC to be corrected.

Description

technical field [0001] The invention relates to the field of analog-to-digital converter design, in particular to a correction method, device, electronic equipment and storage medium for capacitance network mismatch. Background technique [0002] Pipeline ADC (Pipeline Analog-to-Digital Converter) is composed of a pipeline composed of many stages of ADCs. Each stage consists of an ADC, a DAC (digital-to-analog converter), a subtractor, and a residual amplifier, except for the last stage, which requires only one ADC, where the ADC and DAC often use SAR ( Successive ApproximationRegister, successive comparison type) structure. [0003] In the chip manufacturing process, the ratio of the SAR ADC capacitor voltage divider network greatly affects the accuracy of the ADC, and the capacitance value is difficult to measure after the manufacturing is completed, so in order to achieve high precision, it is necessary to improve the circuit structure or use calibration technology. ...

AI Technical Summary

Problems solved by technology

Therefore, the measured weight is a fixed point number, not the true weight, and there is also truncation error, and this error is accumulated when summing

And due to the linearity and gain error of the subsequent SubADC, the measured weight will have a certain deviation from the real weight

Images