Method for manufacturing semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, a method and a structure for forming a barrier-free interconnection layer. The method includes patterning a metal layer disposed over a substrate to form a patterned metal layer, the patterned metal layer including one or more trenches. In some embodiments, the method also includes selectively depositing a barrier layer on the metal surface of the patterned metal layer in the one or more trenches. In some examples, a dielectric layer is deposited in one or more trenches after selective deposition of a barrier layer. Thereafter, the selectively deposited barrier layer may be removed to form an air gap between the patterned metal layer and the dielectric layer.

Description

technical field [0001] Embodiments of the present disclosure relate to semiconductor technologies, and in particular, to semiconductor devices and methods of manufacturing the same. Background technique [0002] The electronics industry is increasingly demanding smaller and faster semiconductor devices capable of supporting more and more complex and sophisticated functions at the same time. Therefore, in the semiconductor industry, it is a continuous trend to manufacture integrated circuits (ICs) with low cost, high performance and low power. To date, these goals have been largely achieved through the miniaturization of semiconductor integrated circuit dimensions (eg, minimum feature size), thereby improving production efficiency and reducing associated costs. However, this device size miniaturization also increases the complexity of the semiconductor manufacturing process. Accordingly, the realization of continued advances in semiconductor integrated circuits and device u...

AI Technical Summary

Problems solved by technology

For example, in some existing metallization techniques, a diffusion barrier (such as TaN) left behind after metallization can lead to increased resistance

Additionally, this diffusion barrier layer can have a high dielectric constant and typically surrounds metal lines and results in increased capacitance

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