FPGA (Field Programmable Gate Array)-based configurable CNN (Convolutional Neural Network) multiplication accumulator supporting 8-bit and 16-bit data

Abstract

The invention discloses an FPGA-based configurable CNN multiply accumulator capable of supporting 8-bit and 16-bit data widths, which comprises a control module, an input feature map register, a weight register, a partial sum register, a PE array and an output feature map register; the control module is used for controlling the time sequence of the whole convolution calculation; the input feature map register is used for registering an input feature map and outputting pixels of the input feature map to the PE array according to a convolution sequence; the weight register is used for providing an input weight for the PE array; the partial sum register is a register array with only one layer, the PE array is used for completing convolution calculation, and the output feature map register is used for registering values obtained after calculation is completed through the PE array. The design and deployment of the CNN hardware accelerator can be accelerated, and the design process is simplified.

Description

technical field [0001] The invention relates to the field of image recognition, in particular to an FPGA-based configurable CNN multiplication accumulator supporting 8-bit and 16-bit data. Background technique [0002] Deep learning is a brand-new field that has developed very rapidly in recent years. As one of the most commonly used models for deep learning, convolutional neural networks are widely used in image processing, face recognition, audio retrieval and other fields due to their excellent feature learning capabilities. . With the development of the convolutional neural network network structure, its network depth continues to deepen, and the network structure is changing with each passing day. The calculation of the network needs to perform a large number of arithmetic operations; at the same time, its application scenarios continue to expand, which puts forward higher requirements for the real-time performance of the network. . In addition, the progress made in n...

AI Technical Summary

Problems solved by technology

[0003] At present, the platforms that can implement CNN mainly include CPU, GPU, FPGA and ASIC. Due to its excellent general performance, CPU is not suitable for computing CNN, which requires a large number of arithmetic operations; GPU, due to its excellent parallel computing capability It is widely used in the training of artificial neural networks, but due to its high power, it is not suitable for use in scenarios that have strict requirements on power; and the cost of GPU is high, so it is mostly used in the cloud at present; On the one hand, it still performs well in terms of cost, but its design threshold is high and the design cycle is long; FPGA is often used for verification before ASIC tape-out due to its programmable characteristics and design close to ASIC, although the energy efficiency of FPGA is not as good as ASIC, But its flexibility to modify the design

[0004] The existing FPGA-based configurable CNN multiplication accumulator can only accelerate some simple calculations with high repeatability, while some complex operations or random logic in CNN, such as the need to calculate the power of the natural number e or some randomness in post-processing Optimization operations such as dropout are difficult to implement with FPGA, or require a lot of resources, and the performance obtained is not directly proportional to the resource investment

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