Chip packaging structure and manufacturing method thereof
A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problems of thicker packaging structure and high process cost, and achieve manufacturing cost saving, small integrated body and effect of weight
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[0076] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or like parts.
[0077] Figure 1A to Figure 1J It is a schematic cross-sectional view of a manufacturing method of a chip packaging structure according to an embodiment of the present invention. Regarding the manufacturing method of the chip packaging structure of this embodiment, first of all, please refer to Figure 1F , providing the carrier 100 formed with a plurality of conductive blocks 210 and at least one metal layer 220 (two metal layers 220 are schematically shown). For details, please refer to Figure 1A , providing a substrate 110 , wherein the substrate 110 includes a core layer 112 , a first conductive layer 114 and a second conductive layer 116 . The first conductive layer 114 and the second...
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