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High-resolution method for synchronously acquiring and analyzing structure and component information of integrated circuit

An integrated circuit and synchronous acquisition technology, applied in the analysis of materials, material analysis using wave/particle radiation, measuring devices, etc., can solve problems such as operational technical difficulties and achieve the effect of deepening understanding

Pending Publication Date: 2021-08-06
苏州鲲腾智能科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Aiming at the deficiencies of the prior art, the present invention provides a high-resolution method for synchronously collecting and analyzing the structure and composition information of integrated circuits. The atomic-level component distribution information and structural information of each functional area of ​​the circuit and the interface between them solves the difficult problem of synchronously collecting and analyzing the atomic-level component distribution while observing the structure

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  • High-resolution method for synchronously acquiring and analyzing structure and component information of integrated circuit

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specific Embodiment approach

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0022] A high-resolution method for synchronously collecting and analyzing integrated circuit structure and composition information, comprising the following steps:

[0023] 1. Using sample thinning equipment to cut and thin the integrated circuit, and prepare thin slices with a thickness of 50nm in the thin area;

[0024] 2. Embed the above-mentioned thin slices on the transmission electron microscope carrier net, which is a semicircular comb shape with a diameter of 3 mm;

...

Embodiment 1

[0029] 1. Preparation of strontium titanate samples that can be used as the interface oxide layer of integrated circuits:

[0030] Focused ion beam equipment is a kind of sample thinning equipment. In this example, it is used to thin strontium titanate, an interface oxide layer commonly used in integrated circuits;

[0031] First, a layer of platinum (Pt) is coated on the selected area to protect the surface of the material, and two "U"-shaped pits are dug with an ion beam at a certain position from the protective layer, and the position of the coated Pt layer (that is, the transmission sample layer) Thinning to about 1.5-2 microns;

[0032] Then the transmission sample layer is connected to the nano-hand through Pt, and the ion beam is used to cut the connection between the transmission sample layer and the original area of ​​the integrated circuit. At this time, the transmission sample layer can be moved by the nano-hand;

[0033] Then use the nano-hand to move the sample t...

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Abstract

The invention relates to the technical field of electron microscopy characterization of integrated circuits, and discloses a high-resolution method for synchronously acquiring and analyzing structure and component information of an integrated circuit, which comprises the following steps: 1, cutting and thinning the integrated circuit by using sample thinning equipment to prepare a thin sheet of which the thickness of a thin area is 50nm; 2, inlaying the prepared thin sheet on a transmission electron microscope carrying net; and 3, observing the selected region in the integrated circuit by using a scanning transmission electron microscope (STEM) function of the high-resolution transmission electron microscope. According to the scheme, a selected area in an integrated circuit is prepared into a thin sheet sample suitable for being observed by a transmission electron microscope by using sample thinning equipment, and the sample is synchronously subjected to high-resolution-level STEM imaging and EDS / EELS acquisition under a high-resolution transmission electron microscope, and structure and component distribution information in the functional regions of the integrated circuit and the interfaces among the functional regions are analyzed and distinguished, so as to analyze the structure-function relationship between the integrated circuit material and the device and the failure reason.

Description

technical field [0001] The invention relates to the technical field of electron microscopy characterization of integrated circuits, in particular to a high-resolution method for synchronously collecting and analyzing the structure and composition information of integrated circuits. Background technique [0002] Today's integrated circuit industry is gradually entering the 2nm process, and will continue to move towards a more refined 1nm process. As the size of integrated circuits decreases, significant changes have taken place in their structural design and production processes. For example, in order to reduce the area of ​​complementary metal oxide semiconductor (CMOS) devices and static random access memory (SRAM), in the 2nm process Forksheet transistors equipped with Buried Power Rail (BPR, the structure of burying power lines under the transistor) are used; in the 1nm process, Complementary FETs (CFETs) using BPR will be used; in order to reduce the The resistance valu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01N23/2206G01N23/20091G01N23/2202G01N23/2273
CPCG01N23/2206G01N23/20091G01N23/2202G01N23/2273
Inventor 刘云龙刘者陈小刚
Owner 苏州鲲腾智能科技有限公司