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Test system for superconducting single-flux quantum circuits

A quantum circuit and test system technology, applied in the direction of electronic circuit test, superconductor element usage, etc., can solve the problems of large-scale chip selection circuit and complicated test steps, and achieve the effect of small scale

Active Publication Date: 2022-07-08
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a test system for a superconducting single magnetic flux quantum circuit, which is used to solve the problems of large-scale chip selection circuits and complicated test steps in the prior art.

Method used

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  • Test system for superconducting single-flux quantum circuits
  • Test system for superconducting single-flux quantum circuits
  • Test system for superconducting single-flux quantum circuits

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0103] like figure 1 and figure 2 As shown, this embodiment provides a test system for a superconducting single magnetic flux subcircuit, and the test system for a superconducting single magnetic flux subcircuit includes:

[0104] The circuit to be tested 2 and at least one chip selection circuit 3 , each of the chip selection circuits 3 and the circuit to be tested 2 are disposed on the same chip 1 .

[0105] like figure 2 As shown, the chip selection circuit 3 receives an input signal, a bias signal, and outputs an output signal, and determines the quality of the current chip based on the test results of each chip selection circuit 3 .

[0106] Specifically, in this embodiment, the chip selection circuit 3 includes a first interface module 3a, a Josephson junction transmission line module 3b and a second interface module 3c. The first interface module 3a receives the input signal in, and transmits the input signal in to the Josephson junction transmission line module 3b...

Embodiment 2

[0109] like figure 1 , Figure 3-Figure 6 As shown, this embodiment provides a testing system for a superconducting single-flux subcircuit, and the difference from the first embodiment is that the chip selection circuit 3 is based on an XNOR linear feedback shift register structure. Linear Feedback Shift Register (LFSR) can be generally divided into XOR type and XNOR type according to the different feedback logic. For multi-bit XOR type LFSR, the circuit is prohibited. The state is the all-zero state of "00...00". When the circuit is working, it is necessary to input a signal to the circuit to introduce a non-zero state, and then the circuit will be in the state of "00...01" to "11...11" Continuous pseudo-random transformation, thereby outputting a pseudo-random sequence at the output, while the same-or LFSR has a similar function, the difference is that the forbidden state of the same-or LFSR is the all-one state of "11...11", while the initial state of the circuit The "00....

Embodiment 3

[0122] like figure 1 , Figure 7-Figure 15 As shown, this embodiment provides a test system for a superconducting single-flux sub-circuit, which is different from the second embodiment in that the chip selection circuit 3 is a high-frequency-based XNOR linear feedback shift register structure.

[0123] like Figure 7 As shown, the chip selection circuit 3 includes a fifth interface module 3k, a sixth interface module 31, a high-frequency clock generation module 3m (Clock Generator, CG), a fourth trigger 3n, a fifth trigger 3o, a sixth trigger 3p, the second XOR gate 3q, the second inverter 3r and the data sampling down-conversion module 3s.

[0124] Specifically, the fifth interface module 3k receives an input signal in (an example is a clock signal), and transmits the input signal in to the high-frequency clock generation module 3m; as an example, the fifth interface module 3k is DC / SFQ converter, converts DC signal to SFQ signal. The bias signal provides bias current fo...

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Abstract

The invention provides a testing system for superconducting single magnetic flux sub-circuits. When the designed circuit is made and taped out, the chip selection circuit and the circuit to be tested are placed on the same chip. The chip selection circuit performs a quick test, and the test result of the chip selection circuit is obtained, which can reflect the quality of the chip, so that the tester can select the circuit with better chip quality to be tested according to the test result of the chip selection circuit. Circuit testing, to save the time used to test the circuit. The present invention designs three different chip selection circuits, which correspond to different circuit testing difficulties respectively, so as to meet the needs of different processes or circuits to be tested. The circuit of the invention only needs three port connections; the circuit test is simple and fast; the circuit scale is small; and the circuit complexity is adjustable.

Description

technical field [0001] The invention relates to the field of superconducting circuits, in particular to a testing system for superconducting single magnetic flux subcircuits. Background technique [0002] Superconducting Single Flux Quantum (SFQ) circuits have the advantages of high speed and low power consumption compared to semiconductor circuits, but superconducting circuits are circuits that work at low temperature (4K), and their tests must also be performed in a low temperature environment. At present, it is impossible to achieve a fully automatic test process similar to semiconductor circuits, and because the development of superconducting circuits is short, the stability of the process cannot be guaranteed, so the test of the circuit is time-consuming. [0003] The basic test process of the superconducting single-flux quantum circuit after the process tape-out is as follows: first, the wafer (wafer) is divided and packaged, and then the PCM circuit (Process Control M...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
CPCG01R31/28Y02E40/60
Inventor 任洁陈理云应利良王镇
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI