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Clock generation circuit and semiconductor apparatus using the clock generation circuit

一种时钟生成电路、时钟的技术，应用在电气元件、功率的自动控制、电数字数据处理等方向，能够解决时钟生成电路需要大量功率、不符合半导体装置低功率等问题

Pending Publication Date: 2021-08-27
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, using a clock generation circuit with high performance may inevitably require a large amount of power, which may not conform to the technological trend of low power for semiconductor devices

Method used

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  • Clock generation circuit and semiconductor apparatus using the clock generation circuit
  • Clock generation circuit and semiconductor apparatus using the clock generation circuit
  • Clock generation circuit and semiconductor apparatus using the clock generation circuit

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0026] Hereinafter, the embodiments are described with reference to the drawings.

[0027] figure 1 is a diagram illustrating the configuration of the clock generation circuit 100 according to the embodiment. refer to figure 1 , the clock generating circuit 100 can generate a plurality of output clock signals by receiving the clock signals CLK and CLKB. The clock generation circuit 100 may include at least two delay loops. At least two delay loops may have different characteristics. At least two delay loops can generate output signals with different characteristics by respectively delaying the received clock signal. One delay loop may consume less power than another delay loop in order to delay the clock signal. Another delay loop may consume more power than one delay loop in order to delay the clock signal. However, another delay loop may generate an output clock signal with higher performance than one delay loop, and that output clock signal has an accurate phase and...

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PUM

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Abstract

The invention relates to a clock generation circuit and a semiconductor apparatus using the clock generation circuit. The clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to Korean Patent Application No. 10-2020-0024488 filed with the Korean Intellectual Property Office on February 27, 2020, the entire contents of which are incorporated herein by reference. technical field [0003] Various embodiments relate generally to integrated circuit technology, and more particularly to clock generation circuits and semiconductor devices using clock generation circuits. Background technique [0004] Electronic equipment includes many electronic components. A computer system of electronic components may include many semiconductor devices configured with semiconductors. Semiconductor devices constituting a computer system can communicate with each other by transmitting and receiving clock signals and data. The semiconductor device can operate in synchronization with a clock signal. The semiconductor device can output or receive data in synchronization with a cloc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/06
CPCH03L7/06H03K5/135H03L7/0818H03L7/07G06F1/3237G06F1/04G06F1/12H03L7/0814H03L7/085H03L7/18H03K5/1565G06F1/10
Inventor 徐荣锡朴奎泰
Owner SK HYNIX INC