Array substrate, array substrate manufacturing method and display panel
An array substrate and substrate technology, applied in semiconductor/solid-state device manufacturing, instruments, electrical components, etc., and can solve problems such as complex processes and numerous film layers
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Embodiment 1
[0052] seefigure 1 , figure 1 It is a schematic diagram of the first structure of the array substrate provided in the embodiment of the present application. The array substrate 10 includes a base 11 , a thin film transistor 20 and a photosensor 100 . The thin film transistor 20 is arranged on the substrate 11, and the thin film transistor 20 includes a gate 22, an active layer 21, a source 23 and a drain 24 connected to the active layer 21; the photosensitive sensor 100 includes a photosensitive module 30 and a memory module 40, and the photosensitive module 30 includes a photosensitive semiconductor layer 31, and the memory module 40 includes a first electrode plate 41 and a second electrode plate 42; wherein, the photosensitive semiconductor layer 31 is arranged on the extension portion 241 of the drain, and the first electrode plate 41 is electrically connected to the photosensitive semiconductor layer 31 away from the side of the extension portion 241 of the drain 24 , the...
Embodiment 2
[0072] see figure 2 , figure 2 The second structure schematic diagram of the array substrate provided by the embodiment of the present application. The array substrate 10 of the embodiment of the present application is the same or similar to that of the first embodiment. The connection relation of the poles 24 is different.
[0073] The first insulating layer includes a fourth via hole 54 through which the second electrode plate 42 is connected to the drain electrode 24 .
[0074] specific, figure 2 The first insulating layer is the covering insulating layer 17 and the flat layer 18. In some cases, the array substrate 10 may only be provided with one of the covering insulating layer 17 and the flat layer 18. At this time, the first insulating layer is the covering insulating layer 17 and one of the flat layers 18.
[0075] In the embodiment of the present application, there is no connection electrode 43 in the first embodiment, and the second electrode plate 42 is direc...
Embodiment 3
[0079] see image 3 , image 3 It is a schematic diagram of the third structure of the array substrate provided by the embodiment of the present application. The array substrate 10 of the embodiment of the present application is the same or similar to the first and second embodiments. The positional relationship between the plate 41 and the second electrode plate 42 is different.
[0080] In the embodiment of the present application, the first insulating layer is disposed on the photosensitive semiconductor layer 31 and the thin film transistor 20 , and the first electrode plate 41 is disposed on the first insulating layer.
[0081] specific, image 3 The first insulating layer is the covering insulating layer 17 and the planar layer 18. In some cases, the array substrate may only be provided with one of the covering insulating layer 17 and the planar layer 18. At this time, the first insulating layer is the covering insulating layer 17. and one of the planar layers 18 .
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