True random number generator and chip

Abstract

The invention belongs to the field of information security chips, and provides a true random number generator and a chip. The true random number generator comprises a plurality of inverter chain channels, a register and an XOR element; each inverter chain channel is used for generating a true random number entropy source; the register is connected in series on each inverter chain channel and is used for synchronizing each true random number entropy source; the XOR element is used for mixing the synchronized true random number entropy sources and then outputting true random numbers; in the inverter chain channels, a switched capacitor assembly is connected in series between any two inverters, and the starting sequence of the switched capacitor assemblies determines the delay time of the ring oscillator formed by the single inverter chain channel.

Description

Technical field

[0001] The present invention belongs to the field of information security chip, in particular to a true random number generator and chip. Background technique

[0002] The statement of this section is merely the background technology information associated with the present invention, which is not necessarily constituted in prior art.

[0003] According to the principles of cryptography, random testing random numbers can be divided into three criteria: 1) statistical pseudo-random; 2) Cryptography secure pseudo-random; 3) true randomness. Pseudo-random number be broken easily, the conventional circuit does not give an efficient and flexible method of increasing the delay of the ring oscillator delay, and a true random number generating circuit TRNG there are not uniform, and the inflexibility problem is not regulated. Inventive content

[0004] In order to solve the technical problems present in the above-described background art, a first aspect of the present inv...

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