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Method for reconstructing parallel substructure of circuit

A technology of parallel sub-structures and circuits, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as limiting the degree of circuit reduction, and achieve the effect of simple process and favorable realization.

Active Publication Date: 2021-09-24
成都华大九天科技有限公司
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  • Application Information

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Problems solved by technology

Therefore, considering the simulation efficiency, if the traditional graph-based search strategy is used to find the parallel substructure, generally only 2-3 levels can be found at most, that is, the number of devices in the parallel unit does not exceed 2 or 3, which limits the degree of circuit reduction.

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  • Method for reconstructing parallel substructure of circuit
  • Method for reconstructing parallel substructure of circuit
  • Method for reconstructing parallel substructure of circuit

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Embodiment Construction

[0035] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0036] figure 1 It is a flow chart of the method for reconstructing the circuit parallel substructure according to the present invention, which will be referred to below figure 1 , to describe in detail the method for reconstructing the circuit parallel substructure of the present invention.

[0037] First, in step 101, the circuit is converted into a bipartite graph.

[0038] At step 102, vertex labels are initialized.

[0039] Preferably, for the device vertices, the graph vertices corresponding to the two devices have the same label, if and only if the two devices are of the same type (such as belonging to linear resistors, or mosfets belonging to the same mo...

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Abstract

The invention discloses a method for reconstructing a parallel substructure of a circuit. The method comprises following steps: 1) converting a circuit into a bipartite graph; 2) initializing vertex marks, and marking node vertexes; 3) performing node vertex clustering according to the marks; 4) performing device vertex clustering according to the marks; 5) checking whether a fixed point is converged, if so, executing the step 6), and otherwise, returning to the step 3); and 6) counting the number of vertexes in each type, and reconstructing a parallel substructure. The method for reconstructing the parallel substructure of the circuit can be effectively applied to reconstructing all parallel substructures with any number of devices and any connection in a large-scale circuit, so that the reduction rate of the circuit is improved, and the simulation performance is improved.

Description

technical field [0001] The invention relates to the technical field of EDA simulation tools, in particular to a method for efficiently reconstructing an arbitrary parallel substructure of a circuit. Background technique [0002] In the process of integrated circuit simulation, in order to reduce the amount of calculation, it is necessary to reduce the circuit in advance, rebuild the parallel substructure of the circuit, and then combine these substructures to effectively achieve the purpose of reduction. In the above process, rebuild the parallel substructure is the core step. The traditional parallel substructure reconstruction algorithm based on graph search is generally only used to identify parallel connections at the device level, that is, if a series of devices have the same type, the same parameters, and the same ports are connected together, these devices are identified as parallel connections. devices as a parallel unit, such as figure 2 shown. However, the paral...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398G06K9/62
CPCG06F30/398G06F2113/18G06F2119/02G06F18/23G06F18/24
Inventor 徐启迪吴大可周振亚
Owner 成都华大九天科技有限公司
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