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Method for forming chip packaging structure

A chip packaging structure and bare chip technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of low yield rate of packaged products, improve product yield, prevent dielectric layer breakage, Avoid the effect of height gap

Pending Publication Date: 2021-10-29
SIPLP MICROELECTRONICS CHONGQING CO LTD
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  • Summary
  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

However, in the actual double-sided wiring process, it is found that the yield of packaged products is low

Method used

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  • Method for forming chip packaging structure
  • Method for forming chip packaging structure
  • Method for forming chip packaging structure

Examples

Experimental program
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Embodiment Construction

[0073] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0074] figure 1 is a flow chart of the method for forming the chip package structure according to the first embodiment of the present invention; Figure 2 to Figure 7 , Figure 9 yes figure 1 The schematic diagram of the intermediate structure corresponding to the process in . Figure 8 is a schematic diagram of the control structure.

[0075] First, refer to figure 1 Step S11 in, figure 2 and image 3 As shown, a carrier board 20 and multiple groups of parts to be molded 1 carried on the carrier board 20 are provided, each group of parts to be molded 1 includes a die 10 and a plurality of first conductive pillars 11, and the die 10 includes an opposite first surface 10a With the second surface 10b, the first conductive pillar 11 i...

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Abstract

The invention provides a method for forming a chip packaging structure, and the method comprises the following steps: after a first rewiring layer is formed, arranging a first support plate on a first dielectric layer covering the first rewiring layer, and arranging a filling layer between a bearing surface of the first support plate and a first electroplating pinch point for electroplating the first rewiring layer. The filling layer can avoid height offset, so that each part of the chip is uniformly stressed in the pressing process, the dielectric layer is prevented from being broken, the photosensitive film is prevented from being infirmly attached or broken, the alignment accuracy during manufacturing of the reverse wiring layer is not influenced, and the product yield is further improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a chip packaging structure. Background technique [0002] In recent years, with the continuous development of circuit integration technology, electronic products are increasingly developing in the direction of miniaturization, intelligence, high integration, high performance and high reliability. [0003] The double-sided wiring process, by performing circuit wiring on both sides of the chip, can improve product integration compared to the single-sided wiring process that only performs wiring on the front side of the chip. However, in the actual double-sided wiring process, it is found that the yield rate of packaged products is low. Contents of the invention [0004] The object of the present invention is to provide a method for forming a chip packaging structure to improve product yield. [0005] In order to achieve the above object, the present ...

Claims

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Application Information

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IPC IPC(8): H01L21/56H01L21/60H01L21/78
CPCH01L21/561H01L24/03H01L21/568H01L21/78H01L24/97H01L2224/0231
Inventor 谭富耀王鑫璐
Owner SIPLP MICROELECTRONICS CHONGQING CO LTD
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