Digital phase discriminator based on finite-state machine

A digital phase detector and finite state machine technology, applied in the direction of automatic power control, electrical components, etc., can solve the problems of shortening the locking time, the identification time of the phase detector is not fast enough, avoiding repeated counting up and working fast , the effect of reducing the number of

Pending Publication Date: 2021-11-09
CHONGQING UNIV OF POSTS & TELECOMM
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  • Application Information

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Problems solved by technology

[0004] Therefore, since the identification time of the current phase detector is not fast enough, a new

Method used

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  • Digital phase discriminator based on finite-state machine
  • Digital phase discriminator based on finite-state machine
  • Digital phase discriminator based on finite-state machine

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[0032] The technical solutions in the embodiments of the present invention will be described in detail below with reference to the drawings in the embodiments of the present invention. The described embodiments are merely a part of the embodiments of the invention.

[0033] The technical solution to solve the above technical problem is:

[0034] See figure 1 The digital correction device implemented by the present invention, includes a first synchronization circuit, a second synchronization circuit, a state machine, a decreasing counter, a storage circuit, the first synchronization circuit, a second synchronization circuit, and a storage circuit connected to the described. The input of the state machine, the add-degrad counter, and the saving circuit connected to the output of the state machine, the add-to-decreasing counter to the saving circuit.

[0035] Specifically, the synchronization circuit is implemented by a pair of D triggers (eg figure 2 As shown), the clock signal can ...

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Abstract

The invention relates to a digital phase discriminator based on a finite-state machine, and the digital phase discriminator comprises a first synchronous circuit, a second synchronous circuit, a state machine, an add-subtract counter and a storage circuit; the first synchronous circuit, the second synchronous circuit and the storage circuit are connected to the input end of the state machine; the add-subtract counter and the storage circuit are connected with the output end of the state machine, and the add-subtract counter is connected with the storage circuit. According to the phase discriminator, signal synchronization processing is carried out on the input signal input by the first synchronous circuit and the feedback signal input by the second synchronous circuit through the first synchronous circuit and the second synchronous circuit, so that the influence of a metastable state condition on an output result of the phase discriminator is avoided; then, under the control of a state machine, corresponding addition or subtraction processing is performed according to different input conditions; and finally, data storage and output are completed through a storage circuit. Through the operation, the output time of the phase discriminator can be effectively shortened, and the power consumption is reduced.

Description

technical field [0001] The invention belongs to the field of integrated circuits, in particular to a digital phase detector circuit based on a state machine control counter. Background technique [0002] The phase-locked loop is a control system that automatically calibrates the phase of the signal. It compares the frequency phase of the external reference clock signal and the feedback clock signal, and generates a clock signal that is consistent with the frequency phase of the reference signal. With the continuous emergence of new materials and new technologies, the level of semiconductor technology has advanced rapidly. The phase-locked loop is composed of independent discrete devices at the beginning, and later developed into an integrated phase-locked loop composed of analog circuits. After entering the nanometer era, the reduction of feature size makes it more and more difficult to improve the performance of analog circuits, and also induces many leakage current proble...

Claims

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Application Information

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IPC IPC(8): H03L7/085
CPCH03L7/085
Inventor 王巍张涛洪赵汝法张珊稅绍林
Owner CHONGQING UNIV OF POSTS & TELECOMM
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