Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The method comprises the steps that: a substrate is provided, a shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure defines a plurality of active regions which are arranged at intervals in the substrate through isolation; a word line groove is formed in the substrate, and the depth of the part, located in the active regions, of the word line groove is smaller than that of the part, located in the shallow groove isolation structure, of the word line groove, so that a first protruding structure is formed at the bottom of the part, located in the active regions, of the word line groove; an etching protection layer is formed on the surface of the first protruding structure; a part of the shallow trench isolation structure is removed, so that a second protruding structure is formed based on the first protruding structure, the upper side wall and the top of the second protruding structure are covered with the etching protection layer, and the lower part of the second protruding structure is exposed by the removed part of the shallow trench isolation structure; the lower part of the second protruding structure is etched, so that the width of the lower part of the second protruding structure is smaller than that of the upper part of the second protruding structure; and a word line structure is formed in the word line groove.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, and in particular, to a semiconductor structure and a preparation method thereof. Background technique [0002] The Shallow Trench Isolation (STI) isolates a number of spaced active areas (AA) in the substrate; the word line structure of the gate of the transistor that can be used as a memory cell intersects with the active area ; The source and drain regions of the transistor are formed in the substrate on both sides of the gate. In a conventional semiconductor process, the word line trenches of the word line structure are formed by one-time etching, and the width of the upper portion and the width of the lower portion of the conductive layer in the word line structure are not significantly different. [0003] However, in the semiconductor device with the above-mentioned word line structure, the channel width of the gate is narrow, and the resistance between the source and...

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Problems solved by technology

[0003] However, the channel width (Channel Width) of the gate in the semiconductor device with the above-mentioned word line structure is narrow, and the resistance between the source and the drain is relatively large, resulting in a small current between the source and the drain during operation. , which affects the performance of the device

In order to increase the channel width of the gate to the required requirement, the overall width of the active region must be increased, and the increase in the width of the active region will cause the spacing between adjacent active regions to be too small, resulting in adjacent active regions. source short circuit

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